Results 1 to 10 of about 146,165 (175)

Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks

open access: yesArray, 2021
In this paper, we present hardware accelerators created with high-level synthesis techniques for sparse and dense matrix multiplication operations. The cores can operate with different precisions and are designed to be integrated in a heterogeneous CPU ...
Jose Nunez-Yanez, Mohammad Hosseinabady
doaj   +1 more source

Area-Efficient Power-Rail ESD Clamp Circuit With False-Trigger Immunity in 28nm CMOS Process

open access: yesIEEE Journal of the Electron Devices Society, 2022
In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid trigger mechanism is proposed and implemented in a 28-nm CMOS process.
Zilong Shen   +3 more
doaj   +1 more source

FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption [PDF]

open access: yesEngineering and Technology Journal, 2010
Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs)are highly attractive options for hardware implementations of encryption algorithmsas they provide cryptographic algorithm agility, physical security, and potentiallymuch higher ...
Ashwaq Talib Hashim   +2 more
doaj   +1 more source

Design and Implementation of Synthesizable VHDL Model for General PCMCIA I/O Cards Controller [PDF]

open access: yesEngineering and Technology Journal, 2008
The portable and nomadic computer market has driven the development ofPCMCIA Cards to address the expansion needs for the user. These cards provide avast variety of hardware devices which are rugged, credit-card sized, lightweight,and power efficient ...
Yousra Abd Mohammed
doaj   +1 more source

Implementing Fuzzy Logic Controller Using VHDL [PDF]

open access: yesEngineering and Technology Journal, 2007
Design of a Fuzzy Logic Controller (FLC) requires more design decisions thanusual, for example rule base, inference engine, defuzzifiction, and data pre- andpost processing.This paper describes a way to implement a simple (FLC) in VHDL, there arethree ...
Yousra A. Mohammed, Leena K. Hashim
doaj   +1 more source

Method of creation of FPGA based implementation of artificial intelligence as a service

open access: yesРадіоелектронні і комп'ютерні системи, 2023
The subject of study in this article is the technologies of Field Programmable Gate Array (FPGA), methods, and tools for prototyping of hardware accelerators of Artificial Intelligence (AI) and providing it as a service. The goal is to reduce the efforts
Artem Perepelitsyn
doaj   +1 more source

High-Performance and Energy-Efficient Fault Tolerance FPGA-to-FPGA Communication [PDF]

open access: yes, 2021
Abstract These days, due to the increasing demand for high speed and parallel computation, several real world applications and systems include multiple FPGAs in them. Due to this, FPGAs often need to communicate among them. So, communication between the FPGAs is one of the key factors that determines the accuracy, performance and correctness of
B. Naresh Kumar Reddy   +3 more
openaire   +1 more source

Penetration testing of FPGA as a Service components for ensuring cybersecurity

open access: yesАвіаційно-космічна техніка та технологія, 2023
The subject of study in this article is modern penetration testing technologies, in which the test object is a platform with access to FPGA resources. The goal of this work is to improve modern methods of penetration testing of services that provide FPGA
Artem Tetskyi
doaj   +1 more source

Design and implementation of partial dynamically reconfigurable FPGA process scheduling

open access: yesDianzi Jishu Yingyong, 2023
In view of the diverse edge computing requirements of the 6G era, reconfigurable technology based on FPGAs can achieve lower latency and provide diversified services.
Qian Hongwen   +5 more
doaj   +1 more source

Constructing cluster of simple FPGA boards for cryptologic computations [PDF]

open access: yes, 2012
In this paper, we propose an FPGA cluster infrastructure, which can be utilized in implementing cryptanalytic attacks and accelerating cryptographic operations.
Doroz, Yarkin   +3 more
core   +1 more source

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