Results 31 to 40 of about 146,240 (250)

Design and Implementation of Programmable Multi-Mode Digital Modulator for SDR Using FPGA [PDF]

open access: yesEngineering and Technology Journal, 2014
The design of programmable multi-mode digital modulator for software defined radio (SDR) technology using FPGA is developed and investigated in this paper.
Majid S. Naghmash
doaj   +1 more source

Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM [PDF]

open access: yes, 2017
This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency ...
A. AMIRA   +27 more
core   +2 more sources

METHOD OF MULTIPARAMETRIZED FPGA-BASED PROJECTS DEVELOPMENT

open access: yesАвіаційно-космічна техніка та технологія, 2018
A classification of project flexibility ways provided in VHDL language is proposed. The results of the analysis of the dependence of the FPGA resources required for the implementation of arithmetic blocks are presented.
Артём Евгеньевич Перепелицын
doaj   +1 more source

Real-Time Information Fusion System Implementation Based on ARM-Based FPGA

open access: yesApplied Sciences, 2023
In this study, an information fusion system displayed fusion information on a transparent display by considering the relationships among the display, background exhibit, and user’s gaze direction. We used an ARM-based field-programmable gate array (FPGA)
Yu-Hsiang Tsai   +4 more
doaj   +1 more source

JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms

open access: yesTransactions on Cryptographic Hardware and Embedded Systems, 2020
After years of development, FPGAs are finally making an appearance on multi-tenant cloud servers. Heterogeneous FPGA-CPU microarchitectures require reassessment of common assumptions about isolation and security boundaries, as they introduce new attack ...
Zane Weissman   +5 more
doaj   +1 more source

Efficient end-to-end long-read sequence mapping using minimap2-fpga integrated with hardware accelerated chaining

open access: yesScientific Reports, 2023
minimap2 is the gold-standard software for reference-based sequence mapping in third-generation long-read sequencing. While minimap2 is relatively fast, further speedup is desirable, especially when processing a multitude of large datasets. In this work,
Kisaru Liyanage   +3 more
doaj   +1 more source

FPGA Realization of Two Different Fractional- Order Time-Delay Chaotic System With Predefined Synchronization Time

open access: yesIEEE Access, 2022
To solve the problem that the fractional-order system is difficult to implement on FPGA, the chaotic behavior of a single fractional-order Chen system is realized on the FPGA platform in this article by using Laplace transform and Bode-domain ...
Lixiong Lin, Qing Wang, Guowei Cai
doaj   +1 more source

SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller [PDF]

open access: yes, 2013
This paper presents an implementation of a neuro-inspired algorithm called VITE (Vector Integration To End Point) in FPGA in the spikes domain. VITE aims to generate a non-planned trajectory for reaching tasks in robots. The algorithm has been adapted
Domínguez Morales, Manuel Jesús   +4 more
core   +1 more source

Rapid prototyping of Networks-on-Chip on multi-FPGA platforms

open access: yesMATEC Web of Conferences, 2016
Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough.
Tan Junyan   +2 more
doaj   +1 more source

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

open access: yes, 2011
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y.   +11 more
core   +1 more source

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