Results 21 to 30 of about 73,618 (259)
Rendering PostScriptTM fonts on FPGAs [PDF]
, 1999 This paper describes how custom computing machines can be used to implement a simple outline font processor. An FPGA based co-processor is used to accelerate the compute intensive portions of font rendering.
Singh, S., Patterson, J., MacVicar, D.
core +1 more source
Design of FPGA online loading based on Flash controller
Dianzi Jishu Yingyong, 2019 Traditional way of FPGA configuration file update is using development tools to write FPGA target code to storage devices such as Nor Flash through the JTAG way.However,when the system becomes complicated with multiple FPGA,it takes a long time to update
Lin Tianjing, Ruan Xiang, Liu Chun
doaj +1 more source
GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms [PDF]
, 2013 We introduce a domain-specific language, GRAph Parallel Actor Language, that enables parallel graph algorithms to be written in a natural, high-level form.
DeLorimier, Michael John
core +1 more source
Method of QoS evaluation of FPGA as a service
Радіоелектронні і комп'ютерні системи, 2022 The subject of study in this article is the evaluation of the performance issues of cloud services implemented using FPGA technology. The goal is to improve the performance of cloud services built on top of multiple FPGA platforms known as FPGA-as-a ...
Artem Perepelitsyn +2 more
doaj +1 more source
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
PGA HPC Implementation of Microtubule Brownian Dynamics Simulations
Труды Института системного программирования РАН, 2018 This paper presents high performance simulation of microtubule molecular dynamics implemented on Xilinx Virtex-7 FPGA using high level synthesis tool Vivado HLS.
Y. A. Rumyanstev +6 more
doaj +1 more source
IET Circuits, Devices and Systems, 2021 This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)‐based applications with simultaneous digital signal processing (DSP) and look‐up‐table (LUT) reduced utilization. The real‐
Mountassar Maamoun +6 more
doaj +1 more source
Авіаційно-космічна техніка та технологія, 2023 The subject of study in this article is modern FPGA technologies for creation of projects and providing them as a services, as well as solutions for ensuring digital rights management of individual instances of the system.
Artem Perepelitsyn
doaj +1 more source
An area-efficient 2-D convolution implementation on FPGA for space applications [PDF]
, 2011 The 2-D Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory.
Stefano Di Carlo +11 more
core +1 more source
PROJETO E IMPLEMENTAÇÃO DE FILTRO DE KALMAN EMBARCADO EM FPGA PARA O RASTREIO DE FOGUETES BALÍSTICOS
Cadernos de Pesquisa, 2014 Neste trabalho faz-se uma abordagem acerca do fiiltro de Kalman no que tange a sua concep-ção, modelamento matemático, algoritmo de fiiltragem e implementação em FPGA (Field Programmable Gate Arrays).
Madson Cruz Machado +2 more
doaj +1 more source