Results 51 to 60 of about 146,240 (250)

From FPGA to Support Cloud to Cloud of FPGA: State of the Art

International Journal of Reconfigurable Computing, 2019
Field Programmable Gate Array (FPGA) draws a significant attention from both industry and academia by accelerating computationally expensive applications and achieving low power consumption.
Rym Skhiri, Virginie Fresse, Jean Paul Jamont, Benoit Suffran, Jihene Malek   +4 more
doaj   +1 more source

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing [PDF]

, 2018
LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow ...
Alvarez, Carlos, Bautista, Leonardo, Becker, Tobias, Billung-Meyer, Gunnar, Carpenter, Paul, Christmann, Wolfgang, Cristal, Adrian, De La Cruz, Raul, Dubhashi, Devdatt, Etsion, Yoav, Felber, Pascal, Fetzer, Christof, Gaydadjiev, Georgi, Göttel, Christian, Hadar, Elad, Hagemeyer, Jens, Jimenez, Daniel, Jungeblut, Thorsten , Kaiser, Martin , Klawonn, Frank, Krupop, Stefan, Kucza, Nils, Madonar, Sergi, Martorell, Xavier, Mihklafi, Amani, Mudge, Trevor, Mudge, Trevor, Pasin, Marcelo, Pericàs, Miquel, Pnevmatikatos, Dionisios N., Porrmann, Mario , Port, Oron, Rocha, Isabelly, Salami, Behzad, Salomonsson, Hans, Schiavoni, Valerio, Trancoso, Pedro, Unsal, Osman S., vor dem Berge, Micha   +38 more
core   +1 more source

Spatial‐Wavelength Multiplexing Error‐Controlled Photonic Analog Computing System

Advanced Science, EarlyView.
A novel photonic integrated circuit prototype implementing the concept of general‐purpose analog computing and demonstrate its capability in radio frequency applications. The chip features a multichannel architecture and performs fully optical analog computation with frequency‐domain parallel processing. An FPGA‐based error‐correction algorithm aims to
Tao Zhu, Bowen Zhu, Shicheng Zhang, Keren Li, Xianchen Wu, Yazhi Pi, Jie Yan, Daigao Chen, Bingli Guo, Xi Xiao, Lei Wang, Xiaochuan Xu, Xuwei Xue, Shanguo Huang, Zizheng Cao, Shaohua Yu   +15 more
wiley   +1 more source

Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

IEEE Access, 2019
Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of Field Programmable Gate Arrays (FPGA) highly ...
Prottay M. Adhikari, Hossein Hooshyar, Luigi Vanfretti   +2 more
doaj   +1 more source

Exploiting partial reconfiguration through PCIe for a microphone array network emulator [PDF]

, 2018
The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization.
Braeken, An, da Silva Gomes, Bruno, Domínguez, Federico, Touhafi, Abdellah   +3 more
core   +2 more sources

An On‐Demand Neuromorphic Vision System Enabled by a Multi‐Paradigm Neuromorphic Device and Hierarchical Reconfigurability Designed from Device to System Level

Advanced Science, EarlyView.
An on‐demand ultra‐reconfigurable intelligent vision system with hierarchical reconfigurability from device to system levels is demonstrated. Through co‐design of a multi‐paradigm device, reconfigurable circuits, and adaptive system architecture/algorithms, the system enables seamless switching among spiking, non‐spiking, neuromorphic imaging (NI), and
Biyi Jiang, Jiayi Xu, Liang Ran, Xinhe Feng, Khalil Harrabi, Yida Li, Longyang Lin, Feichi Zhou   +7 more
wiley   +1 more source

Ensuring cybersecurity of FPGA as a service with the use of penetration testing of components

Радіоелектронні і комп'ютерні системи
The subject of study in this article is modern penetration testing technologies, in which the test object is the implementation of a service based on a platform using Field Programmable Gate Array (FPGA) resources.
Artem Tetskyi, Artem Perepelitsyn, Oleg Illiashenko, Olga Morozova, Dmytro Uzun   +4 more
doaj   +1 more source

PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]

, 2007
We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki, Hamada, Tsuyoshi, Makino, Junichiro   +2 more
core   +2 more sources

3D Large‐Scale Subwavelength‐Resolution Sound Sheet Tomography Based on an Active and Programmable Circular Meta‐Array

Advanced Science, EarlyView.
A programmable 2048‐element circular ultrasound array combined with a compact acoustic lens produces a thin “sound sheet” over a large field of view, and records echoes with wide angular diversity across the ring aperture. Coherence‐enhanced beamforming converts full‐matrix data into high‐contrast tomographic slices, delivering near‐diffraction‐limited
Qiu‐De Zhang, Zi‐Bin Lin, Zhuo Chen, Zhao‐Hui Liu, Jin‐Lian He, Jun‐Jie Song, Long‐Sheng Zeng, Liang Zhou, Ming‐Yue Ding, Yu‐Gui Peng, Ming Yuchi, Xue‐Feng Zhu   +11 more
wiley   +1 more source

Hierarchical Reconfigurable Metasurface Based on Scenario‐Guided Functional Modules and Programmable Core

Advanced Science, EarlyView.
This paper proposes a hierarchical reconfigurable metasurface architecture (HRMA) to achieve comprehensive electromagnetic parameter modulation and on‐demand polymorphic function switching. The reconfigurable metasurface is divided into a programmable core (PC) and scenario‐guided functional modules (FMs), exhibiting significant flexibility and ...
Lihao Zhu, Jiaqi Han, Zhe Zheng, Qiang Feng, Dexiao Xia, Xiangjin Ma, Yajie Mu, Guoliang Luo, Rui Li, Haixia Liu, Hao Xue, Long Li   +11 more
wiley   +1 more source