Results 51 to 60 of about 1,192 (166)

On the Embedded of a Fast, Light and Robust Chaos‐Based Cryptosystem in NEXYS4 FPGA Card for Real Time Color Image Security (CBC in N‐FPGA‐RTCIP)

Engineering Reports, Volume 7, Issue 9, September 2025.
Security evaluation, NPCR + UACI results of 99.5978% and 33.4549% respectively, confirm the system is secure against statistical and differential attacks. Besides, the FPGA implementation achieves low power of 115 mW at a speed of 42.56 MHz. This makes it suitable for IoT applications where power and hardware resources are constrained. ABSTRACT In this
Fritz Nguemo Kemdoum, Gideon Pagnol Ayemtsa Kuete, Serge Raoul Dzonde Naoussi, Justin Roger Mboupda Pone, Wulfran Fendzi Mbasso   +4 more
wiley   +1 more source

Digital Predistorter Implementation for Wideband Power Amplifiers in New Generation Wireless Systems Based on a Low‐Complexity Volterra Series Model

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Volume 38, Issue 5, September/October 2025.
ABSTRACT In this article, we provide a novel, expanded, and adapted pruning approach for the Simplified Volterra Series (SVS) model that makes it applicable to a wider range of Power Amplifiers (PAs). The proposed Modified SVS (MSVS) model is then applied in a Digital Predistortion (DPD) architecture to linearize a 25 W Gallium Nitride (GaN) RF PA.
Haithem Rezgui, Ghalid Abib, Fatma Rouissi, Adel Ghazel   +3 more
wiley   +1 more source

Cadê o Kauê? Co‐design and acceptability testing of a chat‐story aimed at enhancing youth participation in the promotion of mental health in Brazil

Journal of Child Psychology and Psychiatry, Volume 66, Issue 5, Page 697-715, May 2025.
Background Adolescent mental health is vital for public health, yet many interventions fail to recognise adolescents as proactive community contributors. This paper discusses the co‐design and acceptability testing of a chat‐story intervention to enhance Brazilian adolescents' participation in the promotion of mental health in their peer communities ...
Gabriela Pavarini, Sheila Giardini Murta, Josimar Antônio de Alcântara Mendes, Felipe Rodrigues Siston, Rafa Ribeiro Alves de Souza, Rafaela de Oliveira da Cunha, Julyana Alves Ferreira, Victor Hugo de Lima de Santos, Brenda Thallys Rocha Seabra, Talk2U, Nicolás Ferrario, Lu Suarez Battan, Bia Matera, Iasmin Coni, Lucca Rosa Pereira, Thayna Iglesias, Ana Luiza Savi, Daniel Foscarini, Kathia Calil, Felipe Corvello, Sômolo Silvestre Salvador, Amparo Guindón, Silvia Lordello, Larissa Polejack, Alice Christovam Constantino, Alicia Mendes, Ana Clara Freitas Ferreira, Ana Vitória Oliveira da Silva, Brenda lorrane Ferreira Feitosa, Alves, Emerson Gomes dos Santos, Hevellyn Sofia Elvino Pinheiro, Iasmyn Brito dos Santos, Isis Santos Goulart, Jamili Maine Lima Campos, Maria Layza Paixão, Milena Sousa, Mutula Manuel Simão João, Natália Samuel Pitcella Borba, Raissa Barbosa da Silva, Raissa Amarante, Yasmin Bilek, Yasmin Flores da Silva, Gabriela Staerke de Rezende, Jonas de Oliveira Bertucci, Claudia Cavalcante de Carvalho Weber, Janete Araújo da Silva, Rodrigo Araújo Magalhães, Rosimeire Aguiar Pereira Lopes, Mikael Silva Rocha, Ana Paula Santiago S. Andrade, Fernanda Bernardes Silveira Costa, Maria Salete Guerra Maranhão Bezerra, Ilina Singh, Gina Vieira Ponte, Thiago Freire, Tony Marcelo Gomes de Oliveira   +56 more
wiley   +1 more source

e-KiteLab: INVESTIGACIÓN EN FÍSICA APLICADA PARA MANTENIMIENTO Y OPTIMIZACIÓN DE SISTEMAS DE ENERGÍAS RENOVABLES

Investigación & Desarrollo
La investigación tiene como objetivo desarrollar una teoría de aplicabilidad del operador matemático de convolución, como modelador de sistemas físicos. El método comprende un análisis de compatibilidad entre el modelo matemático y las etapas del sistema,
Cecilia Sandoval-Ruiz
doaj   +1 more source

Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

Jurnal Rekayasa Elektrika, 2012
A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others.
. Zulfikar
doaj   +1 more source

Large scale system design aided by modelling and DES simulation: A Petri net approach

Software: Practice and Experience, Volume 55, Issue 2, Page 243-271, February 2025.
Abstract The study of real discrete event systems requires the use of models to cope with complexity and large scale. The only way to understand and analyse their behaviour prior to implementation is, in practice, through distributed simulation. Although it is a widely studied discipline, the difficulty of developing efficient distributed simulation ...
Unai Arronategui, José Ángel Bañares, José Manuel Colom   +2 more
wiley   +1 more source

Cloning and expression of the VHDL receptor from fat body of the corn ear worm, Helicoverpa zea

Journal of Insect Science, 2004
In Noctuids, storage proteins are taken up into fat body by receptor-mediated endocytosis. These include arylphorin and a second, structurally unrelated very high-density lipoprotein (VHDL).
Deryck R. Persaud, Norbert H. Haunerland
doaj  

Purification and properties of the very high density lipoprotein from the hemolymph of adult Triatoma infestans.

Journal of Lipid Research, 1989
The very high density lipoprotein (VHDL) of Triatoma infestans hemolymph from adult males has been isolated and purified by two-step density gradient ultracentrifugation. It appears to be homogeneous as judged by native polyacrylamide gel electrophoresis.
O J Rimoldi, J L Soulages, S M González, R O Peluffo, R R Brenner   +4 more
doaj   +1 more source

FPGAs Implementation of fast algorithms oriented to mp3 audio decompression

Revista Facultad de Ingeniería Universidad de Antioquia, 2012
La ejecución de los algoritmos de descompresión de audio exige procesadores potentes con alto nivel de desempeño, sin embargo, dichos algoritmos no son apropiados para aplicaciones óptimas en dispositivos móviles.
Antonio Benavides, Geovanni Rentería, Álvaro Bernal   +2 more
doaj  

Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim [PDF]

Mehran University Research Journal of Engineering and Technology, 2016
In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code ...
FARIDA MEMON, AAMIR HUSSAIN MEMON, SHAHNAWAZ TALPUR, FAYAZ AHMED MEMON, RAFIA NAZ MEMON   +4 more
doaj