Results 61 to 70 of about 17,348 (175)
CRC 8-bit Encoder-Decoder Component in FPGA using VHDL
Jurnal Elkomika, 2020 AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli.
ANDHI RACHMAN SALEH, SUNNY ARIEF SUDIRO
doaj +1 more source
Generating Logical Architectures from SysML Behavior Models
Systems Engineering, Volume 28, Issue 6, Page 762-778, November 2025.ABSTRACT Modeling solution‐neutral operating principles of system features as SysML behavior models enable systems engineers to specify reusable product features for a variety of similar products and to specify and document a product's functionality in an easy‐to‐understand manner.
Christian Granrath +4 more
wiley +1 more source
Engineering Reports, Volume 7, Issue 10, October 2025.This work presents a secure telemedicine cryptosystem based on a novel 4D memristive chaotic oscillator and a Dispatched Gray Code Scrambler (DGCS). Implemented on FPGA, the system ensures power‐efficient encryption, making it suitable for real‐time medical image transmission in IoT healthcare environments.
Fritz Nguemo Kemdoum +3 more
wiley +1 more source
Um modelo de controle de dispositivos através do barramento PCI: Core PCI [PDF]
, 2003 Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Ciência da Computação.Este trabalho é direcionado ao desenvolvimento de um protocolo PCI, o qual foi aqui denominado, Core PCI. O Core PCI é
Moretti, Alex Sandro
core
Engineering Reports, Volume 7, Issue 9, September 2025.Security evaluation, NPCR + UACI results of 99.5978% and 33.4549% respectively, confirm the system is secure against statistical and differential attacks. Besides, the FPGA implementation achieves low power of 115 mW at a speed of 42.56 MHz. This makes it suitable for IoT applications where power and hardware resources are constrained. ABSTRACT In this
Fritz Nguemo Kemdoum +4 more
wiley +1 more source
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Volume 38, Issue 5, September/October 2025.ABSTRACT In this article, we provide a novel, expanded, and adapted pruning approach for the Simplified Volterra Series (SVS) model that makes it applicable to a wider range of Power Amplifiers (PAs). The proposed Modified SVS (MSVS) model is then applied in a Digital Predistortion (DPD) architecture to linearize a 25 W Gallium Nitride (GaN) RF PA.
Haithem Rezgui +3 more
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An Extended Testing Methodology for VHDL Based High-Level Design
, 1997 An Extended Testing Methodology for VHDL Based High-Level ...
G. Buonanno +4 more
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Investigación & DesarrolloLa investigación tiene como objetivo desarrollar una teoría de aplicabilidad del operador matemático de convolución, como modelador de sistemas físicos. El método comprende un análisis de compatibilidad entre el modelo matemático y las etapas del sistema,
Cecilia Sandoval-Ruiz
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Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code
Jurnal Rekayasa Elektrika, 2012 A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others.
. Zulfikar
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Journal of Child Psychology and Psychiatry, Volume 66, Issue 5, Page 697-715, May 2025.Background Adolescent mental health is vital for public health, yet many interventions fail to recognise adolescents as proactive community contributors. This paper discusses the co‐design and acceptability testing of a chat‐story intervention to enhance Brazilian adolescents' participation in the promotion of mental health in their peer communities ...
Gabriela Pavarini +56 more
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