A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study [PDF]
PeerJ Computer Science, 2020 Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the ...
Varsha Kakkara +5 more
doaj +3 more sources
An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates [PDF]
The Scientific World Journal, 2015 Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority.
T. Kalavathi Devi, Sakthivel Palaniappan
doaj +2 more sources
Constrained coding for error mitigation in nanopore-based DNA data storage [PDF]
Scientific ReportsDNA has been proposed as an alternative to magnetic and solid-state devices for storing digital data. In DNA data storage, writing data is performed through DNA synthesis, and reading is done via sequencing.
Kallie Whritenour +2 more
doaj +2 more sources
IEEE Photonics Journal, 2023 In this article, trellis-coded modulation-enabled probabilistic shaping (TEPS) scheme with a simplified Viterbi decoder is proposed. Trellis-coded modulation (TCM) is embedded in the probabilistic shaping (PS) technique to improve the performance of PS ...
Han Cui +5 more
doaj +1 more source
Degenerate Viterbi Decoding [PDF]
IEEE Transactions on Information Theory, 2013 We present a decoding algorithm for quantum convolutional codes that finds the class of degenerate errors with the largest probability conditioned on a given error syndrome. The algorithm runs in time linear with the number of qubits. Previous decoding algorithms for quantum convolutional codes optimized the probability over individual errors instead ...
Pelchat, Emilie, Poulin, David
openaire +2 more sources
FPGA-based structurally improved(2，1，4) Viterbi decoder
Dianzi Jishu Yingyong, 2020 The implementation of high-performance Viterbi decoding algorithm in resource-constrained processors is a hot topic in recent years. This paper is based on the XC6SLX16-2CSG324 type FPGA processor.
Wu Xueling, Jiang Hong
doaj +1 more source
Recurrent neural network based turbo decoding algorithms for different code rates
Journal of King Saud University: Computer and Information Sciences, 2022 Application of deep learning to error control coding is gaining special attention and neural network architectures on decoding are approached to compare with conventional ones. Turbo codes conventionally use BCJR algorithm for decoding.
Shridhar B. Devamane +1 more
doaj +1 more source
Deep Ensemble of Weighted Viterbi Decoders for Tail-Biting Convolutional Codes
Entropy, 2021 Tail-biting convolutional codes extend the classical zero-termination convolutional codes: Both encoding schemes force the equality of start and end states, but under the tail-biting each state is a valid termination.
Tomer Raviv +2 more
doaj +1 more source
A New Viterbi-Based Decoding Strategy for Market Risk Tracking: an Application to the Tunisian Foreign Debt Portfolio during 2010-2012 [PDF]
Statistika: Statistics and Economy Journal, 2022 In this paper, a novel market risk tracking and prediction strategy is introduced. Our approach takes volatility clustering into account and allows for the possibility of regime shifts in the intra-portfolio's latent correlation structure.
Mohamed Saidane
doaj +1 more source
Comparative Analysis of On-Chip FPGA Memory Architectures for Viterbi Decoder Implementation in DVB Systems [PDF]
JES: Journal of Engineering SciencesHigh-definition Digital Video Broadcasting (DVB) systems demand high data rates, resulting in increased hardware complexity and power consumption, with the Viterbi decoder (VD) being a key contributor.
Asmaa Mosbeh +3 more
doaj +1 more source