Results 11 to 20 of about 62,799 (214)
Performance of Soft Viterbi Decoder enhanced with Non-Transmittable Codewords for storage media
Cogent Engineering, 2018 The introduction of Non-Transmittable Codewords (NTCs) into Viterbi Algorithm Decoder has emerged as one of the best ways of improving performance of the Viterbi Algorithm Decoder.
Kilavo Hassan +2 more
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Interleaved Convolutional Code and Its Viterbi Decoder Architecture [PDF]
EURASIP Journal on Advances in Signal Processing, 2003 We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as
Kong Jun Jin, Parhi Keshab K
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Comparative Analysis of On-Chip FPGA Memory Architectures for Viterbi Decoder Implementation in DVB Systems [PDF]
JES: Journal of Engineering SciencesHigh-definition Digital Video Broadcasting (DVB) systems demand high data rates, resulting in increased hardware complexity and power consumption, with the Viterbi decoder (VD) being a key contributor.
Asmaa Mosbeh +3 more
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A New Viterbi-Based Decoding Strategy for Market Risk Tracking: an Application to the Tunisian Foreign Debt Portfolio during 2010-2012 [PDF]
Statistika: Statistics and Economy Journal, 2022 In this paper, a novel market risk tracking and prediction strategy is introduced. Our approach takes volatility clustering into account and allows for the possibility of regime shifts in the intra-portfolio's latent correlation structure.
Mohamed Saidane
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On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
, 2006 This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system.
Troya, Alfonso +7 more
core +2 more sources
Log-Likelihood Ratio to Improve Hard DecisionViterbi Algorithm [PDF]
Engineering and Technology Journal, 2013 Hard decision of Viterbi decoder suffer from the need of high Signal to Noise Ratio (SNR) to achieve reasonable Bit Error Rate (BER). For the purpose of improving the efficiency of its performance, it must increase the constraint length of the code, in ...
Mahmood Farhan Mosleh, Fa’aza Abid
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Forecasting, 2022 Building a sophisticated forecasting framework for solar and photovoltaic power production in geographic zones with severe meteorological conditions is very challenging.
Joseph Ndong, Ted Soubdhan
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Design of high-speed and low-latency Viterbi decoder
Dianzi Jishu Yingyong, 2018 In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences, namely register exchange method and traceback method.
Yang Min
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Divergence coding for convolutional codes
MATEC Web of Conferences, 2017 In the paper we propose a new coding/decoding on the divergence principle. A new divergent multithreshold decoder (MTD) for convolutional self-orthogonal codes contains two threshold elements.
Valery Zolotarev +4 more
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A high-speed, low-power interleaved trace-back memory for Viterbi decoder [PDF]
, 2006 This paper presents a high-speed, low-power trace-back memory structure for a Viterbi decoder. The new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly.
Israsena, P. +3 more
core +1 more source