Results 1 to 10 of about 425 (179)
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study [PDF]
PeerJ Computer Science, 2020 Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the ...
Varsha Kakkara +5 more
doaj +3 more sources
An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates [PDF]
The Scientific World Journal, 2015 Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority.
T. Kalavathi Devi, Sakthivel Palaniappan
doaj +2 more sources
High performance ACS for Viterbi decoder using pipeline T-Algorithm
AEJ - Alexandria Engineering Journal, 2015 Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to the large number of Trellis transitions.
Dhandapani Vaithiyanathan +1 more
exaly +3 more sources
Constrained coding for error mitigation in nanopore-based DNA data storage [PDF]
Scientific ReportsDNA has been proposed as an alternative to magnetic and solid-state devices for storing digital data. In DNA data storage, writing data is performed through DNA synthesis, and reading is done via sequencing.
Kallie Whritenour +2 more
doaj +2 more sources
IEEE Photonics Journal, 2023 In this article, trellis-coded modulation-enabled probabilistic shaping (TEPS) scheme with a simplified Viterbi decoder is proposed. Trellis-coded modulation (TCM) is embedded in the probabilistic shaping (PS) technique to improve the performance of PS ...
Han Cui +5 more
doaj +1 more source
Degenerate Viterbi Decoding [PDF]
IEEE Transactions on Information Theory, 2013 We present a decoding algorithm for quantum convolutional codes that finds the class of degenerate errors with the largest probability conditioned on a given error syndrome. The algorithm runs in time linear with the number of qubits. Previous decoding algorithms for quantum convolutional codes optimized the probability over individual errors instead ...
Emilie Pelchat, David Poulin
openaire +2 more sources
AN EFFICIENT VITERBI DECODER [PDF]
International Journal of Computer Science, Engineering and Applications, 2012 Convolutional encoding with Viterbi decoding is a good forward error correction technique suitable for channels affected by noise degradation. Fangled Viterbi decoders are variants of Viterbi decoder (VD) which decodes quicker and takes less memory with no error detection capability.
K. S. Arunlal, A. Hariprasad
openaire +3 more sources
Node Synchronization for the Viterbi Decoder [PDF]
IEEE Transactions on Communications, 1984 Motivated by the needs of NASA's Voyager 2 mission, in this paper we describe an algorithm which detects and corrects losses of node synchronization in convolutionally encoded data. This algorithm, which would be implemented as a hardware device external to a Viterbi decoder, makes statistical decisions about node synch based on the hard-quantized ...
Lorden, Gary +2 more
openaire +2 more sources
Recurrent neural network based turbo decoding algorithms for different code rates
Journal of King Saud University: Computer and Information Sciences, 2022 Application of deep learning to error control coding is gaining special attention and neural network architectures on decoding are approached to compare with conventional ones. Turbo codes conventionally use BCJR algorithm for decoding.
Shridhar B. Devamane +1 more
doaj +1 more source
FPGA-based structurally improved(2，1，4) Viterbi decoder
Dianzi Jishu Yingyong, 2020 The implementation of high-performance Viterbi decoding algorithm in resource-constrained processors is a hot topic in recent years. This paper is based on the XC6SLX16-2CSG324 type FPGA processor.
Wu Xueling, Jiang Hong
doaj +1 more source