Results 81 to 90 of about 2,602 (222)

A New Viterbi Algorithm with Adaptive Path Reduction Method [PDF]

, 1993
A new Viterbi algorithm with adaptive path reduction method is presented. The proposed system consists of the pre-decoder and reduced path Viterbi decoder. The predecoder separates the mixed channel noise from the received sequence [6]-[9]. The number of
Yamazato, Takaya, Mori, Shinsaku, Sasase, Iwao   +2 more
core  

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

The Scientific World Journal, 2015
Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority.
T. Kalavathi Devi, Sakthivel Palaniappan
doaj   +1 more source

Performance Analysis of Turbo Codes

Communications, 2013
The article focuses on the performance analyses of Turbo Codes. These codes belong to the group of error correction codes. By their use, it is possible to achieve high system performance.
Jakub Sedy, Pavel Silhavy, Ondrej Krajsa, Ondrej Hrouza   +3 more
doaj   +1 more source

Efficient hardware implementation of a full COFDM processor with robust channel equalization and reduced power consumption

Revista Facultad de Ingeniería Universidad de Antioquia, 2013
This work presents the design of a 12 Mb/s Coded Orthogonal Frequency Division Multiplexing (COFDM) baseband processor for the standard IEEE 802.11a. The COFDM baseband processor was designed by using ourdesigned circuits for carrier phase correction ...
Alexander López Parrado, Jaime Velasco Medina, Julián Adolfo Ramírez Gutiérrez   +2 more
doaj   +1 more source

Viterbi Decoding with Dual Timescale Traceback Processing

, 2007
In this paper a new approach to traceback processing in Viterbi decoders is presented. The approach reduces memory requirements as compared to previous approaches by using different speeds during acquisition of the best trellis path and the subsequent ...
Heinrich Meyr, Olaf J. Joeressen
core  

FPGA Implementation of Convolutional Code Encoding and Viterbi Decoding Algorithm [PDF]

, 2005
探讨了卷积码编码及其Viterbi译码算法的FPGA(Field-ProgrammableGateArray)实现,根据编码器的结构,分别采用了有限状态机转换的编码法和基于流水线结构的状态转换译码法,有效地提高了编译码的速度。最后给出了(2,1,2)卷积码的编码及其Viterbi译码算法的实验仿真结果。FPGA Implementation of Convolutional Code encoding and Viterbi Decoding Algorithm is presented ...
温学东
core  

Minimum decoding trellis length and truncation depth of wrap-around Viterbi algorithm for TBCC in mobile WiMAX

EURASIP Journal on Wireless Communications and Networking, 2011
The performance of the wrap-around Viterbi decoding algorithm with finite truncation depth and fixed decoding trellis length is investigated for tail-biting convolutional codes in the mobile WiMAX standard. Upper bounds on the error probabilities induced
Liu Yu-Sun, Tsai Yao-Yu
doaj  

A Novel High-Speed Configurable Viterbi Decoder for Broadband Access

EURASIP Journal on Advances in Signal Processing, 2003
A novel design and implementation of an online reconfigurable Viterbi decoder is proposed, based on an area-efficient add-compare-select (ACS) architecture, in which the constraint length and traceback depth can be dynamically reconfigured.
Benaissa Mohammed, Zhu Yiqun
doaj   +1 more source

VITURBO: A Reconfigurable Architecture for Viterbi and Turbo Decoding

, 2003
Conference PaperA runtime reconfigurable architecture for high speed Viterbi and Turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying ...
Cavallaro, Joseph R., Vaya, Mani
core   +1 more source

Poster Sessions

HemaSphere, Volume 10, Issue S1, June 2026.
wiley   +1 more source