Results 11 to 20 of about 47,374 (229)

Neuromorphic Analogue VLSI [PDF]

Annual Review of Neuroscience, 1995
Neuromorphic systems emulate the organization and function of nervous systems. They are usually composed of analogue electronic circuits that are fabricated in the complementary metal-oxide-semiconductor (CMOS) medium using very large-scale integration (VLSI) technology.
Douglas, Rodney, Mahowald, Misha, Mead, Carver   +2 more
openaire   +3 more sources

Systematic construction of finite state automata using VLSI spiking neurons [PDF]

, 2012
Spiking neural networks implemented using electronic Very Large Scale Integration (VLSI) circuits are promising information processing architectures for carrying out complex cognitive tasks in real-world applications.
Neftci, Emre, Emre Neftci, Chicca, Elisabetta, Lepora, Nathan F., Rodney Douglas, Prescott, Tony J., Giacomo Indiveri, Verschure, Paul F. M. J., Jonathan Binas, Elisabetta Chicca, Binas, Jonathan, Indiveri, Giacomo, Mura, Anna, Chicca, Elisabetta ; https://orcid.org/, Douglas, Rodney   +14 more
core   +1 more source

Characterizing the firing properties of an adaptive analog VLSI neuron [PDF]

, 2004
Ben Dayan Rubin D, Chicca E, Indiveri G. Characterizing the firing properties of an adaptive analog VLSI neuron. Biologically Inspired Approaches to Advanced Information Technology.
Ben Dayan Rubin, D., Indiveri, G., Giacomo Indiveri, Daniel Ben Dayan Rubin, Elisabetta Chicca, Chicca, Elisabetta ; https://orcid.org/   +5 more
core   +1 more source

Artificial cognitive systems: From VLSI networks of spiking neurons to neuromorphic cognition [PDF]

, 2009
Neuromorphic engineering (NE) is an emerging research field that has been attempting to identify neural types of computational principles, by implementing biophysically realistic models of neural systems in Very Large Scale Integration (VLSI) technology.
Douglas, R J, Chicca, E, Douglas, R. J., Douglas, Rodney J., Indiveri, G, Indiveri, G., Indiveri, Giacomo, Chicca, Elisabetta, Chicca, Elisabetta ; https://orcid.org/   +8 more
core   +1 more source

A systematic method for configuring VLSI networks of spiking neurons [PDF]

, 2011
Neftci E, Chicca E, Indiveri G, Douglas RJ. A systematic method for configuring VLSI networks of spiking neurons. Neural Computation. 2011;23(10):2457-2497.An increasing number of research groups are developing custom hybrid analog/digital very large ...
Rodney Douglas, Chicca, E, Douglas, R. J., Neftci, E, Indiveri, G., Indiveri, G, Giacomo Indiveri, Elisabetta Chicca, Emre Neftci, Chicca, Elisabetta ; https://orcid.org/, Douglas, R, Neftci, E., Neftci E, Neftci, Emre, Chicca E, Indiveri G, Chicca, Elisabetta, Douglas R, Indiveri, Giacomo, Douglas, Rodney   +19 more
core   +1 more source

Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays [PDF]

, 2012
Axonal delays are used in neural computation to implement faithful models of biological neural systems, and in spiking neural networks models to solve computationally demanding tasks. While there is an increasing number of software simulations of spiking
Sadique Sheik, Sheik, S., Sheik, Sadique, Indiveri, G., Giacomo Indiveri, Elisabetta Chicca, Chicca, Elisabetta, Indiveri, Giacomo, Chicca, Elisabetta ; https://orcid.org/   +8 more
core   +1 more source

A VLSI neuromorphic device for implementing spike-based neural networks [PDF]

, 2011
Indiveri G, Chicca E. A VLSI neuromorphic device for implementing spike-based neural networks. Presented at the Proceedings of the 21st Italian Workshop on Neural Nets (WIRN).We present a neuromorphic VLSI device which comprises hybrid analog/digital ...
Morabito, C. F., Indiveri, G., Apolloni, B., Esposito, A., Chicca, Elisabetta ; https://orcid.org/, Bassis, S.   +5 more
core   +1 more source

MIMO detection in analog VLSI [PDF]

, 2006
In this paper we propose an analog VLSI approach to maximum a posteriori (MAP) detection in multiple-input multiple-output (MIMO) systems. This detector can be seen as an extension of the well known analog decoding concept for error correcting codes, as ...
McNamara, DP, Soler Garrido, J, Piechocki, RJ, Maharatna, K, R.J. Piechocki, K. Maharatna, D. McNamara, J. Soler-Garrido   +7 more
core   +1 more source

FPGA-based fault injection design for 16K-point FFT processor

The Journal of Engineering, 2019
There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao, Yu Xie, Xin Wei, Yi-Zhuang Xie, He Chen   +4 more
doaj   +1 more source

An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor

Memories - Materials, Devices, Circuits and Systems, 2023
In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications. In this paper, an energy-efficient 10T SRAM-based IMC macro architecture is proposed to perform logic, arithmetic, and In ...
Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal   +2 more
doaj   +1 more source