Results 31 to 40 of about 121,840 (219)
Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology
Advanced Intelligent Discovery, EarlyView.Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh +3 more
wiley +1 more source
IEEE Access, 2019 Fine-grained task models can exploit parallelism to achieve high performance for multiprocessor system-on-chip (MPSoC). However, fine-grained models face the issues of high-communication overhead and difficult scheduling decisions, and the two challenges
Kai Huang +6 more
doaj +1 more source
, 2013 We report a resistance based threshold logic family useful for mimicking brain like large variable logic functions in VLSI. A universal Boolean logic cell based on an analog resistive divider and threshold logic circuit is presented.
Francis, L. R. V. J. +2 more
core +1 more source
A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems [PDF]
, 2007 We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained ...
Costas Santos, Jesús +3 more
core +1 more source
A New Strategy to Design Reconfigurable Rivest–Shamir–Adleman (RSA) Accelerators
International Journal of Circuit Theory and Applications, EarlyView.A reconfigurable FPGA‐based RSA accelerator is proposed using compression‐based modular multipliers combined with pseudomoduli arithmetic. The approach maps modular exponentiation to low‐cost arithmetic domains and applies a correction stage, achieving significant improvements in delay, operating frequency, and delay–area efficiency compared with ...
Augusto C. B. Vassoler +4 more
wiley +1 more source
IEEE Access, 2018 Energy saving and system reliability are two crucial issues for designing modern multiprocessor systems. There has been reliability-aware power management with dynamic voltage-frequency scaling (DVFS) schemes in recent studies.
Kai Huang +6 more
doaj +1 more source
IEEE Access, 2020 This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency.
Zunsong Yang +4 more
doaj +1 more source
A Rectangular Area Filling Display System Architecture [PDF]
, 1982 A display system architecture which has rectangular area filling as its primitive operation is presented. It is shown that lines can be drawn significantly faster while rendition of filled boxes shows an O(n^2) speed improvement.
Whalen, Daniel S
core +1 more source
International Journal of Circuit Theory and Applications, EarlyView.This work explores the conversion from residues to binary representation in RNS using the Chinese remainder theorem (CRT) or mixed radix conversion (MRC) algorithms. The proposed approach relocates CRT multiplicative inverses to the arithmetic stage without extra cost, improving scalability while achieving speedups over state‐of‐the‐art MRC ...
Gabriel B. M. Fernandes +2 more
wiley +1 more source
Accurate Line Reconstruction for Point and Line-Based Stereo Visual Odometry
IEEE Access, 2019 The point feature is widely used in feature-based visual simultaneous localization and mapping (V-SLAM) or visual odometry (VO) systems, whereas the line feature is rarely explored even though it is more robust and contains more structural information ...
Xiaohua Luo, Zhitao Tan, Yong Ding
doaj +1 more source