Results 61 to 70 of about 121,840 (219)
Design Of Neural Network Circuit Inside High Speed Camera Using Analog CMOS 0.35 ¼m Technology [PDF]
Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed
Mukhlis, Yulisdin
core
Proposed active rectifier solution, detailing the high‐side and low‐side power switch control circuit for implementing the active diodes. ABSTRACT This paper proposes a novel active rectifier architecture for wireless power transfer (WPT) systems. In addition to performing rectification, the proposed structure features embedded current monitoring ...
Elisabetta Moisello +3 more
wiley +1 more source
Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits
This work begins by outlining the fundamental concepts of MTJs, FinFETs, and the conventional hybrid CMOS/MTJ framework. It then explains the operating mechanism and configuration of the proposed STT‐MTJ/FinFET‐based OR logic gate. The final sections present the simulation outcomes and analyze the influence of FinFET fin variation.
Pillem Ramesh, Atul S. M. Tripathi
wiley +1 more source
Seizure Prediction Using Multi-View Features and Improved Convolutional Gated Recurrent Network
Epilepsy is one of the most common neurological diseases worldwide. Early prediction of seizure onsets is of great significance for the safety of intractable epilepsy patients. This work aims to develop a reliable and accurate method for patient-specific
Lihan Tang +3 more
doaj +1 more source
Architecture for VLSI design of Reed-Solomon encoders [PDF]
The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that
Liu, K. Y.
core +1 more source
Universality for Graphs of Bounded Degeneracy
ABSTRACT Given a family ℋ$$ \mathscr{H} $$ of graphs, a graph G$$ G $$ is called ℋ$$ \mathscr{H} $$‐universal if G$$ G $$ contains every graph of ℋ$$ \mathscr{H} $$ as a subgraph. Following the extensive research on universal graphs of small size for bounded‐degree graphs, Alon asked what is the minimum number of edges that a graph must have to be ...
Peter Allen +2 more
wiley +1 more source
Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator
Low-voltage delta–sigma modulators (DSMs) have broad application prospects in power-constrained sensor systems but with undeveloped energy efficiency.
Weiqiang Chen +3 more
doaj +1 more source
Parallel VLSI architecture emulation and the organization of APSA/MPP [PDF]
The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation.
Odonnell, John T.
core +1 more source
k-way Hypergraph Partitioning via n-Level Recursive Bisection
We develop a multilevel algorithm for hypergraph partitioning that contracts the vertices one at a time. Using several caching and lazy-evaluation techniques during coarsening and refinement, we reduce the running time by up to two-orders of magnitude ...
Henne, Vitali +5 more
core +1 more source
Metal‐assisted chemical etching without an oxidant? We report an unexpected Cu2+‐catalyzed anisotropic etching of silicon in HF–HCl solutions. Despite the low redox potential of Cu2+, pyramidal surface structures are generated without a distinctive additional oxidizing agent.
Florian Honeit +5 more
wiley +1 more source

