Results 61 to 70 of about 47,374 (229)

Automated Heartbeat Classification Exploiting Convolutional Neural Network With Channel-Wise Attention

open access: yesIEEE Access, 2019
Long-term Electrocardiogram (ECG) analysis has become a common means of diagnosing cardiovascular diseases. In order to reduce the workload of cardiologists and accelerate diagnosis, an automated patient-specific heartbeat classification method based on ...
Feiteng Li   +4 more
doaj   +1 more source

A Lossless Electrocardiogram Compression System Based on Dual-Mode Prediction and Error Modeling

open access: yesIEEE Access, 2020
Long-term electrocardiogram (ECG) monitoring requires high-ratio lossless compression techniques to reduce data transmission energy and data storage capacity.
Menghan Jia   +3 more
doaj   +1 more source

Two Self‐Stabilizing Algorithms for the Maximal Pentagon Partitioning Problem

open access: yesConcurrency and Computation: Practice and Experience, Volume 38, Issue 19, October 2026.
ABSTRACT Given an undirected graph G=(V,E)$$ G=\left(V,E\right) $$, a collection of disjoint subsets of nodes π={V1,…,Vk}(V=V1∪⋯∪Vk)$$ \pi =\left\{{V}_1,\dots, {V}_k\right\}\kern0.3em \left(V={V}_1\cup \cdots \cup {V}_k\right) $$ is called a pentagon partition if each subset Vi(1≤i≤k)$$ {V}_i\kern0.3em \left(1\le i\le k\right) $$ satisfies one of the ...
Tota Yamada   +2 more
wiley   +1 more source

Si1−xGex nanowire based metal‐semiconductor‐metal Schottky biristor: Design and sensitivity analysis

open access: yesIET Circuits, Devices and Systems, 2021
The incorporation of Si1−xGex nanowire based metal‐semiconductor‐metal (MSM) Schottky biristor allows the conceptualization and realization of low latch‐up and latch‐down voltages with retained latching window.
Shaleen Nr, Sangeeta Singh, Pankaj Kumar
doaj   +1 more source

On the Design of a Class of Analog Filters Whose Impulse Response Is a Mittag‐Leffler Function

open access: yesInternational Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5173-5182, October 2026.
Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known forms are summarized in this work. Simulation results using Cadence and experimental results using an FPAA validate the introduced concept. ABSTRACT Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known
Julia Nako   +3 more
wiley   +1 more source

Context dependent amplification of both rate and event-correlation in a VLSI network of spiking neurons [PDF]

open access: yes, 2007
Chicca E, Indiveri G, Douglas RJ. Context dependent amplification of both rate and event-correlation in a VLSI network of spiking neurons. Presented at the Advances in Neural Information Processing Systems 19 (NIPS).Cooperative competitive networks are ...
Schölkopf, B.   +5 more
core  

Analog VLSI Design Automation

open access: yes, 2003
The explosive growth and development of the integrated circuit market over the last few years have been mostly limited to the digital VLSI domain. The difficulty of automating the design process in the analog domain, the fact that a general analog design
Günhan Dündar   +5 more
core   +1 more source

ECG Authentication Method Based on Parallel Multi-Scale One-Dimensional Residual Network With Center and Margin Loss

open access: yesIEEE Access, 2019
To enhance the security level of digital information, the biometric authentication method based on Electrocardiographic (ECG) is gaining increasing attention in a wide range of applications.
Yifan Chu, Haibin Shen, Kejie Huang
doaj   +1 more source

Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization

open access: yesInternational Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5045-5061, October 2026.
This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley   +1 more source

Online VLSI Testing

open access: yesIEEE Design & Test of Computers, 1998
International ...
Karri, R., Nicolaidis, M.
openaire   +3 more sources

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