Results 71 to 80 of about 47,374 (229)

Carbon Nanotube Based Variation Tolerant Low Power Cache Memory for 5G Networks [PDF]

Iranian Journal of Electrical and Electronic Engineering
The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power.
Kavitha Manickam, P.K. Janani, S. Karthick, S. Arulsivam, C. Vikram, G. Hariharan, R. Kavinkumar, P. Ganesh   +7 more
doaj  

Parallel Multi‐Operand Addition Using CPA‐Trees and Carry‐Select Adders

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5140-5147, October 2026.
A balanced parallel CPA‐tree architecture with CSLA reduces the critical‐path delay of multi‐operand addition while preserving structural regularity. ASIC results demonstrate delay reductions of up to 34% with low area overhead, providing an efficient and scalable solution for high‐performance arithmetic.
Lucas R. Kieslich, Oldemir Chiocchetta Júnior, Fabian Leonardo Cabrera, Hector Pettenghi   +3 more
wiley   +1 more source

A Comparative Analysis of Very-Large-Scale Integration and Embedded Systems: Technologies, Applications and Future Trends

ES General
The rapid advancement of modern electronics has led to the widespread use of Very-Large-Scale Integration (VLSI) and Embedded Systems, both of which are pivotal in the development of high-performance, energy-efficient, and cost-effective hardware ...
G. Sarkar, S. Bachhar, S. K. Biswas, J. Pandit   +3 more
doaj   +1 more source

An Ultra‐Low‐Power Biopotential Acquisition Analog Front‐End Chip for Wearable Devices

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5030-5044, October 2026.
A 0.8‐V, 1.2‐μW biopotential AFE combines a chopper‐stabilized CCIA with dual‐time‐scale EDO management. The slow DSL preserves > 1 GΩ input impedance, whereas an event‐triggered fast‐recovery path shortens return to the linear range after abrupt electrode‐offset disturbances. ABSTRACT A 0.8‐V, 1.2‐μW biopotential analog front‐end (AFE) IC is presented
Zhang Xin, Yang Tianqi, Xu Wei, Wang Shun, Xiaoxi Ma   +4 more
wiley   +1 more source

Contraction Properties of VLSI Cooperative Competitive Neural Networks of Spiking Neurons [PDF]

, 2008
Neftci E, Chicca E, Indiveri G, Slotine J-J, Douglas R. Contraction Properties of VLSI Cooperative Competitive Neural Networks of Spiking Neurons. Presented at the Advances in Neural Information Processing Systems 20 (NIPS), Vancouver, British Columbia ...
Douglas, R., Indiveri, G., Koller, D., Chicca, Elisabetta ; https://orcid.org/, Slotine, J.-J., Singer, Y., Roweis, S., Neftci, E., Platt, J.C.   +8 more
core  

A Code‐Invariant QSG–VGA Co‐Design Methodology for Compact CMOS Vector‐Sum Phase Shifters

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 5165-5172, October 2026.
A circuit‐level co‐design methodology for compact vector‐sum phase shifters is presented, combining a code‐invariant common‐gate variable‐gain amplifier (VGA) with a resistorless quadrature signal generator (QSG). By maintaining an almost constant input resistance, explicit resistors are eliminated from the QSG.
Uxua Esteban Eraso, Carlos Sánchez‐Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma   +4 more
wiley   +1 more source

Systematic configuration and automatic tuning of neuromorphic systems [PDF]

, 2011
In the past recent years several research groups have proposed neuromorphic Very Large Scale Integration (VLSI) devices that implement event-based sensors or biophysically realistic networks of spiking neurons.
Sheik, S., Neftci, E, Indiveri, G, Fabio Stefanini, Emre Neftci, Sheik, S, Sadique Sheik, Chicca, E, Stefanini, F., Indiveri, G., Giacomo Indiveri, Elisabetta Chicca, Chicca, Elisabetta ; https://orcid.org/, Neftci, E., Stefanini, F   +14 more
core   +1 more source

Simplified Small‐Signal Modeling Method for Non‐Isolated High Step‐Up Converters

International Journal of Circuit Theory and Applications, Volume 54, Issue 10, Page 4859-4875, October 2026.
A generalized small‐signal modeling methodology for a family of non‐isolated high step‐up DC‐DC converters is proposed. ABSTRACT This work presents a generalized small‐signal modeling methodology for a family of DC–DC converters based on the four‐state switching cell with a wide conversion range (WCR‐4SSC) operating in continuous conduction mode (CCM).
Samuel Antonio Macedo de Oliveira, Pedro Herysson Almeida da Silva, Fernando Lessa Tofoli, Dalton de Araújo Honório   +3 more
wiley   +1 more source

Emergent auditory feature tuning in a real-time neuromorphic VLSI system [PDF]

, 2012
Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic ...
Martin eCoath, Giacomo eIndiveri, Elisabetta eChicca, Sadique Sheik, Martin Coath, Wennekers, Thomas, Chicca, E, Susan L Denham, Thomas eWennekers, Elisabetta Chicca, Chicca, Elisabetta ; https://orcid.org/, Coath, Martin, Indiveri, G, Indiveri, Giacomo; id_orcid, Denham, Susan L., Coath, M, Chicca, Elisabetta, Sheik, S, Sadique eSheik, Denham, S L, Sheik, Sadique, Wennekers, T, Giacomo Indiveri, Susan L. Denham, Indiveri, Giacomo, Thomas Wennekers, Indiveri G, Wennekers T, Coath M, Denham SL, Chicca E, Sheik S   +31 more
core   +1 more source

Obfuscation of combination circuits of digital devices from unauthorized access

Informatika, 2019
The problems of designing modern VLSI and SoC are analyzed. The most difficult problems of design are problems of verification of projects at different stages of design.
L. A. Zolotorevich
doaj