Results 71 to 80 of about 120,677 (152)
An implementation of a broadband model for the generation of an accurate time‐domain description of parasitic elements from frequency‐domain electromagnetic (EM) simulator results is proposed. It is designed to work simultaneously at low and high frequencies, bypassing EM simulators limitations, validating it against measurement and presenting a ...
Silvia Simone +3 more
wiley +1 more source
Additive effects under the series of EOS in space application VLSI circuits
One of the problems of space technology is the spacecraft on orbit charging effect. Series of EOS (electrical overstress) are caused by internal charging affect VLSI (very large-scale integrated) circuits, which may lead to its damage. The results of the
Diatlov Nikolai +2 more
doaj +1 more source
A Systematic Review of Compressive Sensing: Concepts, Implementations and Applications
Compressive Sensing (CS) is a new sensing modality, which compresses the signal being acquired at the time of sensing. Signals can have sparse or compressible representation either in original domain or in some transform domain.
Meenu Rani, S. B. Dhok, R. B. Deshmukh
doaj +1 more source
On testing VLSI chips for the big Viterbi decoder [PDF]
A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing.
Hsu, I. S.
core +1 more source
Design and Implementation of BCM Rule Based on Spike-Timing Dependent Plasticity
The Bienenstock-Cooper-Munro (BCM) and Spike Timing-Dependent Plasticity (STDP) rules are two experimentally verified form of synaptic plasticity where the alteration of synaptic weight depends upon the rate and the timing of pre- and post-synaptic ...
Abbott, Derek +3 more
core +1 more source
Wet‐Chemical Etching of Silicon Wafer Surfaces Using Aqueous HF‐HBrO3 and HF‐HBrO3‐Br2 Solutions
Aqueous mixtures of HF and HBrO3 are reported as a new NOx‐free etching systems for monocrystalline silicon wafers. Silicon is polished with etching rates up to 10 µm min−1 at room temperature. The addition of Br2 leads to anisotropic etching, thus texturing monocrystalline silicon wafer surfaces with upright pyramids.
Nils Schubert +7 more
wiley +1 more source
This manuscript finds that the previous impedance modeling and stability analysis methods for photovoltaic inverters have not yet considered the fractional‐order characteristics of the elements; in order to make up for the blank in this research field, this paper carried out relevant work.
Guanlei Li +4 more
wiley +1 more source
Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System
The world of 3D graphic computing has undergone a revolution in the recent past, making devices more computationally intensive, providing high-end imaging to the user. The OpenGL ES Standard documents the requirements of graphic processing unit.
Avni Agarwal +3 more
doaj +1 more source
Architecture for VLSI design of Reed-Solomon encoders [PDF]
The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that
Liu, K. Y.
core +1 more source
From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula [PDF]
© 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions.
Gupta, Navarun +3 more
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