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Doping-Less Feedback Field-Effect Transistors. [PDF]

Micromachines (Basel)
Kim H, Lim D.
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A capacitor-less 1T-DRAM cell

IEEE Electron Device Letters, 2002
A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8F/sup 2/ 1T/1C DRAM cell and the process of its manufacturing does not require ...
S. Okhonin, M. Nagoga, J.M. Sallese, P. Fazan   +3 more
exaly   +2 more sources

A New 1T DRAM Cell: Cone Type 1T DRAM Cell

IEICE Transactions on Electronics, 2011
We propose a new cone-type DRAM cell as a 1T DRAM cell. The superiority of cone shape is already reported, in that the electric field concentration effect encourages impact ionization phenomenon. So the device has improved DRAM characteristics compared with cylinder type 1T DRAM Cell (SGVC Cell).
Gil Sung LEE, Doo-Hyun KIM, Seongjae CHO, Byung-Gook PARK   +3 more
openaire   +1 more source

Junction Engineering of 1T-DRAMs

IEEE Electron Device Letters, 2013
One-transistor dynamic random access memories (DRAMs) (1T-DRAMs) are considered a promising candidate to overcome the limits of scalability of conventional one-transistor/one-capacitor DRAMs. Robust and reproducible operation has been demonstrated by experiments in MOSFET devices with a gate length (L) down to ~50 nm, which prevents their use in future
GIUSI, Gino, Iannaccone G.
openaire   +3 more sources

1T-DRAM With Shell-Doped Architecture

IEEE Transactions on Electron Devices, 2019
This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use
Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti   +3 more
openaire   +1 more source

Capacitorless 1T-DRAM on Crystallized Poly-Si TFT

Journal of Nanoscience and Nanotechnology, 2011
The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser ...
Min Soo, Kim, Won Ju, Cho
openaire   +2 more sources

A SOI capacitor-less 1T-DRAM concept

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2002
A simple 1T DRAM cell concept is proposed for the first time. It exploits the body charging of PD SOI devices to store the information. This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor.
S. Okhonin, M. Nagoga, J.M. Sallese, P. Fazan   +3 more
openaire   +1 more source

Low-Power Z2-FET Capacitorless 1T-DRAM

2017 IEEE International Memory Workshop (IMW), 2017
This work highlights the features of Z2-FET capacitorless 1T-DRAM describing its operation in detail. The Z2-FET memory cell fabricated with FDSOI technology delivers large current sense margin along with long retention time at room temperature. Numerous measurements confirm that the demonstrated 1T-DRAM is able to achieve attractive current margin ...
Parihar, Mukta Singh, Lee, Kyung Hwa, El Dirani, Hassan, Navarro, Carlos, Lacord, Joris, Martinie, Sébastien, Barbé, Jean-Charles, Fonteneau, Pascal, Galy, Philippe, Le Royer, Cyrille, Mescot, Xavier, Gamiz, Francisco, Cheng, Binjie, Asenov, Asen, Taur, Yuan, Bawedin, Mayline, Cristoloveanu, Sorin   +16 more
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Split-Gate-Structure 1T DRAM for Retention Characteristic Improvement

Journal of Nanoscience and Nanotechnology, 2011
As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical ...
Garam, Kim, Sang Wan, Kim, Kyung-Chang, Ryoo, Jeong-Hoon, Oh, Min-Chul, Sun, Hyun Woo, Kim, Dae Woong, Kwon, Ji Soo, Jang, Sunghun, Jung, Jang Hyun, Kim, Byung-Gook, Park   +10 more
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Physical Insights on BJT-Based 1T DRAM Cells

IEEE Electron Device Letters, 2009
The basic operation of BJT-based floating-body 1T DRAM cells on SOI is analyzed with supportive numerical device simulation. Extreme sensitivity of the charging process (write ldquo1rdquo) to the offset (Deltat WB) between the word-line and bit-line voltage pulses is revealed and explained.
null Zhenming Zhou, J.G. Fossum, null Zhichao Lu   +2 more
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