Results 1 to 10 of about 18,499 (235)
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process [PDF]
IEEE Access, 2021 As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased.
Ki Chul Chun, Kyomin Sohn, Sungho Kang
exaly +4 more sources
DCA: a DRAM-Cache-Aware DRAM Controller [PDF]
SC16: International Conference for High Performance Computing, Networking, Storage and Analysis, 2016 3D-stacking technology has enabled the option of embedding a large DRAM cache onto the processor. Since the DRAM cache can be orders of magnitude larger than a conventional SRAM cache, the size of its cache tags can also be large.
Vijay Nagarajan +5 more
core +3 more sources
Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case [PDF]
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015 In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee re-liable operation.
Donghyuk Lee +6 more
core +2 more sources
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017 Initializing memory with zero data is essential for safe memory management. However, initializing a large memory area slows down the system significantly. The most likely cause for initialization to slow down the system is the limited DRAM initialization
Shin, Wongyu +11 more
core +2 more sources
DRAM‐4 and DRAM‐5 are compensatory regulators of autophagy and cell survival in nutrient‐deprived conditions [PDF]
FEBS Journal, 2022 Macroautophagy is a membrane-trafficking process that delivers cytoplasmic material to lysosomes for degradation. The process preserves cellular integrity by removing damaged cellular constituents and can promote cell survival by providing substrates for
Valentin J A Barthet +2 more
exaly +2 more sources
Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM
Micromachines, 2020 Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM).
Hyeonjeong Kim +2 more
exaly +3 more sources
Ramulator: A Fast and Extensible DRAM Simulator
IEEE Computer Architecture Letters, 2016 Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as ...
Yoongu Kim, Onur Mutlu
exaly +2 more sources
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips.
Ataberk Olgun +2 more
exaly +2 more sources
Design of a gate-all-around arch-shaped tunnel-field-effect-transistor-based capacitorless DRAM [PDF]
Discover NanoIn this study, we designed and analyzed a single-transistor dynamic random-access memory (1 T-DRAM) based on an arch-shaped gate-all-around tunnel field-effect transistor (GAA ARCH-TFET), featuring an Si/SiGe heterostructure, for high-density memory ...
Seung Ji Bae +9 more
doaj +2 more sources
Novel three-dimensional stacked capacitorless DRAM architecture using partially etched nanosheets for high-density memory applications [PDF]
Discover NanoThis study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs.
Min Seok Kim +9 more
doaj +2 more sources