Results 1 to 10 of about 503 (134)
DRAM Retention Behavior with Accelerated Aging in Commercial Chips
The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities.
Md Kawser Bepary +2 more
exaly +4 more sources
An Experimental Analysis of RowHammer in HBM2 DRAM Chips
To appear at DSN Disrupt ...
Ataberk Olgun +2 more
exaly +3 more sources
Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology [PDF]
We propose an ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry (IMMSE) system for semiconductor metrology. The IMMSE system achieves large-area measurements with a 20 mm × 20 mm field of view (FOV)—the largest FOV reported to date—and a
Juntaek Oh +14 more
doaj +2 more sources
arXiv
Ataberk Olgun +2 more
exaly +5 more sources
DLL Design with Wide Input Duty Cycle Range and Low Output Clock Duty Cycle Error [PDF]
This paper presents the design of a Delay-Locked Loop (DLL) with a simple architecture and a wide input clock duty cycle range. The design is tailored to meet the increasing data rate and stringent clock requirements of modern semiconductor chips, with ...
Binyu Qin +4 more
doaj +2 more sources
RowPress Vulnerability in Modern DRAM Chips
Memory isolation is a critical property for system reliability, security, and safety. We demonstrate RowPress, a DRAM read disturbance phenomenon different from the well-known RowHammer. RowPress induces bitflips by keeping a DRAM row open for a long period of time instead of repeatedly opening and closing the row.
Haocong Luo +2 more
exaly +3 more sources
Performance Analysis Of SRAM and Dram in Low Power Application [PDF]
All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of
Yuvaraj S. +5 more
doaj +1 more source
Addressing multiple bit/symbol errors in DRAM subsystem [PDF]
As DRAM technology continues to evolve towards smaller feature sizes and increased densities, faults in DRAM subsystem are becoming more severe. Current servers mostly use CHIPKILL based schemes to tolerate up-to one/two symbol errors per DRAM beat. Such
Ravikiran Yeleswarapu, Arun K. Somani
doaj +2 more sources
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process
As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased.
Jaewon Park +5 more
doaj +1 more source
Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling
Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental ...
Deepak M. Mathew +5 more
doaj +1 more source

