Results 11 to 20 of about 941 (185)

RowPress: Amplifying Read Disturbance in Modern DRAM Chips

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and closing (i.e., hammering) a DRAM row many times causes bitflips in physically nearby rows.
Haocong Luo, Ataberk Olgun, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Steve Rhyner, Meryem Banu Cavlak, Joël Lindegger, Mohammad Sadrosadati, Onur Mutlu   +8 more
openaire   +3 more sources

Understanding Latency Variation in Modern DRAM Chips [PDF]

ACM SIGMETRICS Performance Evaluation Review, 2016
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses; (ii) precharge, which prepares the cell array for the next memory access; and (iii) restoration of ...
Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li, Gennady Pekhimenko, Samira Khan, Onur Mutlu   +9 more
openaire   +3 more sources

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips

CoRR, 2018
This article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which was published in SIGMETRICS 2016, and examines the work's significance and future potential.
Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li 0001, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu   +9 more
openaire   +3 more sources

Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips

CoRR
Increasing storage density exacerbates DRAM read disturbance, a circuit-level vulnerability exploited by system-level attacks. Unfortunately, existing defenses are either ineffective or prohibitively expensive. Efficient mitigation is critical to ensure robust (reliable, secure, and safe) execution in future DRAM-based systems.
Yağlıkçı, Abdullah Giray
openaire   +3 more sources

Low-Voltage and High-k Properties of Bilayer HZO Capacitors at the Morphotropic Phase Boundary for Next-Generation Memory Applications. [PDF]

Adv Sci (Weinh)
The HfxZr1‐xO2‐based ferroelectric/antiferroelectric bilayer capacitor exhibits morphotropic‐phase‐boundary behavior with a high dielectric constant (∼52) at 2 V. Phase engineering stabilizes o/t‐phase coexistence and suppresses m‐phase formation, enabling capacitance enhancement and self‐optimization under cycling for scalable low‐voltage, high‐κ ...
Kim J, Park H, Han C, Shin H, Choi M, Shin C.   +5 more
europepmc   +2 more sources

CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention

IEEE Access, 2020
Row-hammering flips bits in a victim DRAM row by frequently activating its adjacent rows, compromising DRAM integrity. Several studies propose to prevent row-hammering by counting the number of activates to a DRAM row and refreshing the corresponding ...
Ingab Kang, Eojin Lee, Jung Ho Ahn
doaj   +1 more source

OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems

Sensors, 2021
With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5.
Duy-Thanh Nguyen, Nhut-Minh Ho, Weng-Fai Wong, Ik-Joon Chang   +3 more
doaj   +1 more source

Enhancing the security of memory in cloud infrastructure through in‐phase change memory data randomisation

IET Computers & Digital Techniques, 2021
As a promising alternative to dynamic RAM, phase change memory (PCM) suffers from limited write endurance. Therefore, many research proposals on PCM security or reliability have focussed on the possible threat of wear‐out attacks from malicious ...
Xianzhong Zhou, Ying Wang
doaj   +1 more source

PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures

IEEE Access, 2019
Physically unclonable functions (PUFs) are potential security blocks to generate unique and more secure keys in low-cost cryptographic applications. Dynamic random-access memory (DRAM) has been proposed as one of the promising candidates for generating ...
B. M. S. Bahar Talukder, Biswajit Ray, Domenic Forte, Md Tauhidur Rahman   +3 more
doaj   +1 more source

Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

IEEE Open Journal of Nanotechnology, 2020
Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time (Tret).
Hyangwoo Kim, Hyeonsu Cho, Byoung Don Kong, Jin-Woo Kim, Meyya Meyyappan, Chang-Ki Baek   +5 more
doaj   +1 more source