Results 31 to 40 of about 941 (185)

A Novel In-DRAM Accelerator Architecture for Binary Neural Network

, 2020
We propose a novel computation-in-memory (CIM) architecture based on DRAM for binary neural network, in which a novel charge sharing circuit enables us to perform all logic operations and accumulation inside sub-array at a very small area overhead (1.22%)
Choi, Haerang, Lee, Yosep, Yoo, Sungjoo, Jae-Joon Kim, Yosep Lee, Sungjoo Yoo, KIM, JAE JOON, Haerang Choi   +7 more
core   +1 more source

Neuromorphic Electronics for Intelligence Everywhere: Emerging Devices, Flexible Platforms, and Scalable System Architectures

Advanced Materials, EarlyView.
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj, Roshni Satheesh Babu, Yuxin Xia, Eva Bestelink, Radu Sporea, Nikos Hastas, Ioannis Zeimpekis, Dimitra G. Georgiadou, Sayani Majumdar   +8 more
wiley   +1 more source

A Performance Comparison of Contemporary DRAM Architectures [PDF]

, 1999
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study of a representative group, each evaluated in a small ...
Bruce Jacob, Davis, Brian, Trevor Mudge, Mudge, Trevor, Cuppu, Vinodh, Jacob, Bruce, Brian Davis, Vinodh Cuppu   +7 more
core   +2 more sources

Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices

IEEE Journal of the Electron Devices Society, 2016
Electronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power ( $\text{P}_{\mathrm{ DC}}$ )
Paul R. Berger, Albert Chin, Akira Nishiyama, Meikei Ieong   +3 more
doaj   +1 more source

Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology [PDF]

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), 2000
A field-programmable multi-chip module containing one ORCA 3T/125 FPGA and 4 MByte DRAM was built using chip-on-chip technology. Module architecture and physical design issues are presented. A PCI board consisting of four chip-on-chip modules is also built as the test vehicle.
Michael X. Wang, Katsuharu Suzuki, Wayne W.-M. Dai, Yee L. Low, Kevin J. O'conner, King L. Tai   +5 more
openaire   +1 more source

Self‐Powered Bearing Sensing and Real‐Time Fault Diagnosis Enabled by Non‐Invasive Triboelectric Sensors and Edge AI Acceleration

Advanced Science, EarlyView.
This study achieves the synergistic integration of self‐powered sensing and edge AI acceleration to establish a real‐time fault diagnosis system. The proposed TENG‐based self‐powered bearing sensor (NSE‐TBS) and FPGA‐accelerated edge AI framework fundamentally break through the inherent limitations of conventional monitoring systems, including complex ...
Kehui Zhu, Zhongheng Liu, Xinming Li, Jinrui Zhang, Meng Li, Yiming Guo, Lihua Han, Yanxue Wang   +7 more
wiley   +1 more source

Impact of body biasing on the retention time of gain-cell memories

The Journal of Engineering, 2013
Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM).
Pascal Meinerzhagen, Adam Teman, Alexander Fish, Andreas Burg   +3 more
doaj   +1 more source

Photonic‐Enabled Energy‐Efficient Transparent Neuromorphic Computing Devices: A Review

Advanced Science, EarlyView.
Transparent photonic neuromorphic computing devices merge optics and brain‐inspired computing to overcome von Neumann bottlenecks with ultrafast, low‐energy processing. By exploiting transparent oxides, 2D materials, phase‐change materials, and hybrid heterostructures, these platforms enable photonic synapses, memory, and logic for see‐through edge ...
Shuvaraj Ghosh, Ki‐bum Lee, Junghyeon Lee, Seunghee Cho, Malkeshkumar Patel, Hangfei Li, Yu Wen, Ye Zhou, Joondong Kim   +8 more
wiley   +1 more source

Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks

Advanced Electronic Materials, EarlyView.
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley   +1 more source

3D Network-On-Chip With On-Chip Dram: An Empirical Analysis For Future Chip Multiprocessor

, 2010
With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale ...
Xu, Thomas Canhao, Yang, Bo, Yin, Alexander Wei, Liljeberg, Pasi, Tenhunen, Hannu   +4 more
openaire   +2 more sources