Results 21 to 30 of about 941 (185)

Balancing the Lifetime and Storage Overhead on Error Correction for Phase Change Memory. [PDF]

PLoS ONE, 2015
As DRAM is facing the scaling difficulty in terms of energy cost and reliability, some nonvolatile storage materials were proposed to be the substitute or supplement of main memory.
Ning An, Rui Wang, Yuan Gao, Hailong Yang, Depei Qian   +4 more
doaj   +1 more source

Efficiency balanced matrix transpose method for sliding spotlight SAR imaging processing

The Journal of Engineering, 2019
Matrix transposition is a very critical operation in synthetic aperture radar (SAR) imaging systems. This study presents an improved corner turning memory solution for real-time SAR imaging processing.
Tianyuan Sun, Yizhuang Xie, Bingyi Li
doaj   +1 more source

Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case [PDF]

, 2015
In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee re-liable operation.
Donghyuk Lee, Gennady Pekhimenko, Onur Mutlu, Yoongu Kim, Samira Khan, Kevin Chang, Vivek Seshadri   +6 more
core   +1 more source

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

, 2021
54th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2021 -- 18 October 2021 through 22 October 2021 -- 172825ARM;et al.;Huawei;IBM;Intel;MicrosoftRowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e ...
Onur Mutlu, Yağlıkçı, A. Giray, Hasan Hassan, Olgun, Ataberk, Haocong Luo, Jisung Park, Lois Orosa, Orosa, L., Luo, H., Hassan, H., Patel, M., Abdullah Giray Yaglikci, Park, J., Minesh Patel, Ataberk Olgun, Jeremie S. Kim   +15 more
core   +1 more source

A Novel Chip-Level Blockchain Security Solution for the Internet of Things Networks

Technologies, 2019
The widespread computer network has been changing drastically and substantially since blockchain and IoT entered the stage. Blockchain is good at protecting data transactions between logical nodes with a desirable guaranty.
Hiroshi Watanabe, Howie Fan
doaj   +1 more source

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

, 2021
ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) -- JUN 14-19, 2021 -- ELECTR NETWORKTrue random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases ...
Onur Mutlu, Ergin, Oğuz, Yağlıkçı, A. Giray, Nandita Vijaykumar, Olgun, Ataberk, Haocong Luo, Oguz Ergin, Bostancı, F. Nisa, Patel, Minesh, Luo, Haocong, A. Giray Yaglikci, Minesh Patel, Ataberk Olgun, Jeremie S. Kim, Vijaykumar, Nandita, F. Nisa Bostanci   +15 more
core   +1 more source

Hira: Hidden Row Activation for Reducing Refresh Latency of Off-The Dram Chips

, 2022
Yaglikci, Abdullah Giray/0000-0002-9333-6077; Ergin, Oguz/0000-0003-2701-3787DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss.
Patel, Minesh, Yaglikci, A. Giray, Luo, Haocong, Mutlu, Onur, Orosa, Lois, Hassan, Hasan, Olgun, Ataberk   +6 more
core   +1 more source

SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature Variations

IEEE Access
RowHammer is a DRAM vulnerability that can cause bit errors in a victim DRAM row solely by accessing its neighboring DRAM rows at a high-enough rate. Recent studies demonstrate that new DRAM devices are becoming increasingly vulnerable to RowHammer, and ...
Lois Orosa, Ulrich Ruhrmair, A. Giray Yaglikci, Haocong Luo, Ataberk Olgun, Patrick Jattke, Minesh Patel, Jeremie S. Kim, Kaveh Razavi, Onur Mutlu   +9 more
doaj   +1 more source

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Journal of Low Power Electronics and Applications, 2014
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior
Pooja Batra, Spyridon Skordas, Douglas LaTulipe, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz, Wei Lin, Tuan Vo, Deepika Priyadarshini, Alex Hubbard, Kristian Cauffman, Brown Peethala, John Barth, Toshiaki Kirihata, Troy Graves-Abe, Norman Robson, Subramanian Iyer   +20 more
doaj   +1 more source

The 2017 IRDS Lithography Roadmap

Journal of Microelectronic Manufacturing, 2018
Technology roadmaps have been a part of the semiconductor industry for many years. The first roadmap was Moore’s law, which started as an empirical observation that competitive forces then turned into a prediction that became an industry roadmap.
Mark Neisser
doaj   +1 more source