Results 41 to 50 of about 941 (185)
Advanced Electronic Materials, EarlyView.In this work, low‐resolution infrared imaging is combined with a 28 nm FeFET IMC architecture to enable compact, energy‐efficient edge inference. MLC FeFET devices are experimentally characterized, and controlled multi‐level current accumulation is validated at crossbar array level.
Alptekin Vardar +9 more
wiley +1 more source
SPICE‐Compatible Compact Modeling of Cuprate‐Based Memristors Across a Wide Temperature Range
Advanced Electronic Materials, EarlyView.A physics‐guided compact model for YBCO memristors is introduced, incorporating carrier trapping, field‐induced detrapping, and a differential balance equation to describe their switching dynamics. The model is compared with experiments and implemented in LTspice, allowing realistic circuit‐level simulations.
Thomas Günkel +6 more
wiley +1 more source
Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case
, 2018 In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation.
Onur Mutlu (5357288) +6 more
core +1 more source
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient in-DRAM Operations
, 2022 The memory controller is in charge of managing DRAM maintenance operations (e.g., refresh, RowHammer protection, memory scrubbing) in current DRAM chips.
Yaglikci, A. Giray +4 more
core +1 more source
Register‐Efficient Linear‐Time Evaluation in the Bernstein Basis
Computer Graphics Forum, EarlyView.Abstract We investigate the evaluation of points and derivatives of Bézier curves and surfaces on modern architectures, focusing on performance and guided by numerical error bounds. While the de Casteljau algorithm remains the reference for numerical robustness, its linear working‐set size imposes substantial register pressure on GPUs.
Gábor Valasek, Anna Lili Horváth
wiley +1 more source
International Journal of Applied Linguistics, EarlyView.ABSTRACT Studies on classroom interactions suggest that displaying affiliation through linguistic and multimodal resources could promote positive emotions like enjoyment, thereby enhancing engagement and enthusiasm in second/foreign language learning.
Karen C. K. Choi, Kevin W. H. Tai
wiley +1 more source
Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors [PDF]
, 2010 DRAM row buffer conflicts can increase the memory access latency significantly for single-threaded applications. In a chip multiprocessor system, multiple applications competing for DRAM will suffer additional row buffer conflicts due to interthread interference.
Wei Mi +3 more
openaire +1 more source
Evolution of Materials and Device Stacks for HfO2‐Based Ferroelectric Memories
Advanced Materials Interfaces, Volume 13, Issue 11, 9 June 2026.This review summarizes engineering strategies for HfO2 based ferroelectric memories with focus on FeCAP and FeFET structures. It describes how dopant design, stress effects, and interface engineering improve the bulk ferroelectric response. It further discusses how channel engineering supports reliable memory characteristics and scalable integration ...
Eunjin Kim, Jiyong Woo
wiley +1 more source
Hydrogen‐State‐Engineered Oxide Semiconductor Channels Enabling Reliable 2T0C DRAM Operation
Advanced Electronic Materials, Volume 12, Issue 11, 8 June 2026.We introduce a three‐step hydrogen annealing method for oxide semiconductor devices that modulates hydrogen incorporation and its passivation behavior. Consequently, interface traps are suppressed, whereas the mobility, reliability, and data retention of the IGO‐based 2T0C DRAM are simultaneously improved.
Jun‐Yeoub Lee +5 more
wiley +1 more source
EMERGING ARCHITECTURES FOR PROCESSOR-IN-MEMORY CHIPS: TAXONOMY AND IMPLEMENTATION
RUDN Journal of Engineering Research, 2016 The emergence of PIM (processing-in-memory) die and Date-Centric systems (DCS) and near- data processing approach (NDP) has given rise to the need of developing architectural taxonomy for multi-core PNM (processing near memory) hardware with multi-level ...
A Lapshinsky Valery
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