Results 61 to 70 of about 941 (185)

Materials for DRAM Memory Cell Applications

, 2022
Semiconductor memory is one of the key technologies driving the success of Si-based information technology within the last five decades. The most prominent representative memory type, the dynamic random access memory(DRAM)was patented in 1967 and was ...
Schroeder, Uwe, Slesazeck, Stefan, Cho, Kyuho   +2 more
core   +1 more source

Reflections on trade policy: Then and now

Canadian Journal of Economics/Revue canadienne d'économique, EarlyView.
Kala Krishna
wiley   +1 more source

FPGA‐accelerated streaming data reduction achieving an average compression ratio over 8000 in a 17.4 kHz, 840 kpixel CITIUS detector for quasi‐elastic gamma‐ray scattering

Journal of Synchrotron Radiation, Volume 33, Issue 3, Page 609-616, May 2026.
A high‐throughput field‐programmable gate array (FPGA)‐accelerated data‐reduction and ‐analysis pipeline combined with high‐performance computing enables the continuous handling of a 216 Gbps data stream from quasi‐elastic gamma‐ray scattering experiments at SPring‐8.We present a data‐acquisition and ‐analysis framework for quasi‐elastic gamma‐ray ...
Haruki Nishino, Masashi Kobayashi, Toshiyuki Nishiyama Hiraki, Yoshiaki Honjo, Kyosuke Ozaki, Mitsuhiro Yamaga, Nobumoto Nagasawa, Yoshitaka Yoda, Yasumasa Joti, Makina Saito, Takaki Hatsui   +10 more
wiley   +1 more source

BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows

, 2021
Aggressive memory density scaling causes modern DRAM devices to suffer from RowHammer, a phenomenon where rapidly activating a DRAM row can cause bit-flips in physically-nearby rows.
Park, Jisung, Onur Mutlu, Roknoddin Azizi, Hasan Hassan, Azizi, Roknoddin, Taha Shahroodi, Orosa, Lois, Olgun, Ataberk, Hassan, Hasan, Saugata Ghose, Jisung Park, Lois Orosa, Konstantinos Kanellopoulos, Yağlıkçı, Abdullah Giray, Patel, Minesh, Ghose, Saugata, Kanellopoulos, Konstantinos, Kim, Jeremie S., Mutlu, Onur, Shahroodi, Taha, A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Ataberk Olgun   +23 more
core   +1 more source

A Vertically Stackable Split‐Gate Amorphous Oxide Semiconductor 2T0C DRAM for Reducing Capacitive Coupling and Sneak‐Path Current

Advanced Materials Technologies, Volume 11, Issue 7, 6 April 2026.
A split‐gate amorphous oxide semiconductor (AOS) 2T0C DRAM effectively suppresses capacitive coupling and sneak‐path currents that occur in conventional 2T0C designs using a split‐gate read transistor. It shows a high on/off ratio, long retention time, and multiple conductance states.
Jeong‐Min Lee, Seung‐Yoon Lee, Seong‐Jun Byun, Joon‐Kyu Han   +3 more
wiley   +1 more source

PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips

Proceedings of the 52nd Annual International Symposium on Computer Architecture
Processing-using-DRAM (PuD) is a promising paradigm for alleviating the data movement bottleneck using a DRAM array's massive internal parallelism and bandwidth to execute very wide dataparallel operations. Performing a PuD operation involves activating multiple DRAM rows in quick succession or simultaneously, i.e., multiple-row activation.
Ismail Emir Yuksel, Akash Sood, Ataberk Olgun, Oguzhan Canpolat, Haocong Luo, Nisa Bostanci, Mohammad Sadrosadati, A. Giray Yaglikçi, Onur Mutlu   +8 more
openaire   +3 more sources

Design Considerations of Die-Stacked DRAM Caches [PDF]

, 2016
Multiple-channel die-stacked DRAMs have been used for maximizing the performance and minimizing the power of memory access in 2.5D/3D system chips. Stacked DRAM dies can be used as a cache for the processor die in 2.5D/3D system chips.
Wang, Rou-Li Melody, Li, Jin-Fu, Yu, Yun-Chao   +2 more
core  

Understanding and Improving the Latency of DRAM-Based Memory Systems

, 2018
Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory ...
Kevin K. Chang (5469251)
core   +1 more source

SCALE DRAM Subsystem Power Analysis [PDF]

, 2005
To address the needs of the next generation of low-power systems, DDR2 SDRAM offers a number of low-power modes with various performance and power consumption tradeoffs. The SCALE DRAM Subsystem is an energy-aware DRAM system with various system policies
Vimal Bhalodia
core   +1 more source

Analysis and prevention of DRAM latch-up during power-on

, 2019
The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented, Through HSPICE simulations and measurements,
Park, KW, Oh, CS, Kim, YH, Oh, JH, Park, HJ, Sim, JY, Chung, HW, Doh, JI, Ahn, SH   +8 more
core   +1 more source