Results 51 to 60 of about 941 (185)
Atomic Layer Deposition in Transistors and Monolithic 3D Integration
Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu +5 more
wiley +1 more source
Multi-Gigabyte On-Chip DRAM Caches for Servers
While DRAM latency has long been recognized as a major bottleneck in servers, DRAM bandwidth is emerging as an important bottleneck as server processors shift to many-core architectures to allow for sustainable throughput improvements. The rapid expansion of the digital universe, increasingly stored in memory, rapidly pushes the need for higher DRAM ...
openaire +1 more source
Ferroelectric HfO2/ZrO2 Superlattice Capacitors With High Center to Edge Wafer‐Scale Uniformity
“Enhanced wafer‐scale device uniformity on 150 mm wafers is demonstrated using ferroelectric superlattice HfO2/ZrO2 (HZO) capacitors, as compared to conventional solid solution HZO capacitors. Superlattice HZO exhibits improved ferroelectric memory properties, including a broader polarization window, greater endurance, reduced leakage, and superior ...
Oscar Kaatranen +4 more
wiley +1 more source
Razavi, Kaveh/0000-0002-8588-7100;The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die ...
Onur Mutlu +11 more
core +1 more source
Crystal IO FETs feature (1) extremely low off current and (2) high on current. For ultralow‐power consumption, we are aiming at replacing conventional memories by crystal IO‐based memories and ultralow‐power ALUs using AiMC FETs in the subthreshold regime. This report will introduce the trend of these technologies.
Shunpei Yamazaki +27 more
wiley +1 more source
Mingzhi Dai1,2, Yongbin Hu,3 Changhe Huo,1 Thomas J Webster,4 Liqiang Guo31Ningbo Institute of Materials and Technology Engineering, Chinese Academy of Sciences, Beijing 315201, People’s Republic of China; 2Center of Materials Science and ...
Dai M, Hu Y, Huo C, Webster TJ, Guo L
doaj
This project aims to develop novel frame buffer pixel circuit-based silicon backplanes using 180 nm process technology for polarization-independent liquid crystal on silicon (PI-LCOS) phase modulators.
Qirui Zhang +3 more
doaj +1 more source
Views from the hill: Deer stalkers' perspectives on land‐use change in the Scottish Highlands
Abstract Land‐use and wildlife management are changing globally as part of efforts to address contemporary environmental challenges. In the Scottish Highlands, the hunting—or ‘stalking’—of deer has entered a period of considerable flux primarily because of national policy changes to mitigate climate change and biodiversity loss.
Callum Leavey‐Wilson +2 more
wiley +1 more source
Interface Engineering of Chip Surfaces via Silane Treatments for Robust Underfill Adhesion
Void formation at underfill–solder bump interfaces requires complex process control and extended thermal exposure, limiting the reliability of advanced semiconductor packaging. To overcome this limitation, direct organosilane surface modification is selected to enable uniform interfacial wetting while preserving underfill integrity, offering a reliable
Zambaga Otgonbayar +8 more
wiley +1 more source
A DRAM Centric NoC Architecture and Topology Design Approach [PDF]
Most communication traffic in today’s System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM controller.
De Micheli, Giovanni +10 more
core +1 more source

