Results 71 to 80 of about 941 (185)
Development of 3D-Packaging Process Technology for Stacked Memory Chips
, 2006 A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package.
Osamu Kato +14 more
core +1 more source
Simultaneous Many-Row Activation in Off-The Dram Chips: Experimental Characterization and Analysis
King Abdullah University of Science and Technology; Resilient Computing and Cybersecurity Center54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2024 -- 24 June 2024 through 27 June 2024 -- Brisbane -- 202203We ...
Oliveira, G.F. +6 more
core +1 more source
Architectural Techniques to Enhance DRAM Scaling
, 2018 For decades, main memory has enjoyed the continuous scaling of its physical substrate: DRAM (Dynamic Random Access Memory). But now, DRAM scaling has reached a threshold where DRAM cells cannot be made smaller without jeopardizing their robustness.
Yoongu Kim (2269069)
core +1 more source
ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality [PDF]
, 2016 DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism,called ChargeCache, that enables faster access to recently accessed rows in DRAM, with no modifications to DRAM chips.
Donghyuk Lee +13 more
core +1 more source
, 2022 The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row
van der Veen, Victor +5 more
core
Concurrent Autonomous Self-Test for Uncore Components in System-on-Chips
, 2018 Concurrent autonomous self-test, or online self-test, allows a system to test itself, concurrently during normal operation, with no system downtime visible to the end-user. Online self-test is important for overcoming major reliability challenges such as
Yanjing Li (5357837) +3 more
core +1 more source
DRAM-level prefetching for fully-buffered DIMM: Design, performance and power saving
, 2007 We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core proces-sors. FB-DIMM has a unique two-level interconnect structure, with FB-DIMM channels at the first-level connecting the mem-ory controller and ...
Hongzhong Zheng +4 more
core +1 more source
Retrospective: RAIDR: Retention-Aware Intelligent DRAM Refresh
, 2023 Dynamic Random Access Memory (DRAM) is the prevalent memory technology used to build main memory systems of almost all computers. A fundamental shortcoming of DRAM is the need to refresh memory cells to keep stored data intact.
Mutlu, Onur
core
, 2023 Our ISCA 2014 paper provided the first scientific and detailed characterization, analysis, and real-system demonstration of what is now popularly known as the RowHammer phenomenon (or vulnerability) in modern commodity DRAM chips, which are used as main ...
Mutlu, Onur
core
Understanding Reduced-Voltage Operation in Modern DRAM Devices
, 2017 The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy ...
Aditya Agrawal +9 more
core +1 more source