Results 91 to 100 of about 941 (185)

Hybrid-gate MoS₂ 2T0C DRAM for low-power multi-bit storage with high linearity. [PDF]

Natl Sci Rev
Zhang Z, Gou S, Song Y, Dong X, Zhu Y, Sun Z, Ao M, Sun Q, Zhang J, Hu Y, Tian Y, Chen H, He X, Shang J, Chen Q, Liu Y, Xia Y, Yang C, Meng H, Liu M, Li H, Wang Y, Zhou P, Bao W.   +23 more
europepmc   +1 more source

Design and Simulation of a Hierarchical Parallel Distributed Processing Model for Orientation Selection Based on Primary Visual Cortex. [PDF]

Biomimetics (Basel), 2023
Wei H, Ye J, Li J, Wang Y.
europepmc   +1 more source

Oxide semiconductor gain cell-embedded memory: materials and integration strategies for next generation on-chip memory. [PDF]

Commun Eng
Chung SW, Yoon SH, Jeong JK.
europepmc   +1 more source

ADPO: Adaptive DRAM Controller for Performance Optimization. [PDF]

Micromachines (Basel)
Liu Z, Li Y, Zeng X.
europepmc   +1 more source

HBM Package Interconnection Pseudo All-Channel Signal Integrity Simulation and Implementation Method of the Synchronous Current Load Research. [PDF]

Micromachines (Basel)
Tang WX, Mai CJ, Zhou LY, Sun Y, Zhao XR, Liu SL, Wang G, Wang DW, Wang CQ.   +8 more
europepmc   +1 more source

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions. [PDF]

Micromachines (Basel), 2022
Tian W, Li B, Li Z, Cui H, Shi J, Wang Y, Zhao J.   +6 more
europepmc   +1 more source

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands

The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enhance reliability, and mitigate security vulnerability.
Wi, Minbok, Song, Chihun, Ahn, Jung Ho, Nam, Hwayong, Baek, Seungmin, Kim, Michael Jaemin, Kim, Nam Sung, Park, Jaehyun   +7 more
core  

in situ Transformation of Information Into DNA Storage With Microfluidic Very Large-Scale Integration Platform. [PDF]

Small
Liu DD, Ngang SWY, Cheow LF.
europepmc   +1 more source

A tri-linear quantum dot architecture for semiconductor spin qubits. [PDF]

Sci Rep
Li R, Levajac V, Godfrin C, Kubicek S, Simion G, Raes B, Beyne S, Fattal I, Loenders A, De Roeck W, Mongillo M, Wan D, De Greve K.   +12 more
europepmc   +1 more source

Low-Power-Management Engine: Driving DDR Towards Ultra-Efficient Operations. [PDF]

Micromachines (Basel)
Liu Z, Li Y, Zeng X.
europepmc   +1 more source