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Inverted bit‐line sense amplifier with offset‐cancellation capability

Electronics Letters, 2016
An inverted bit‐line sense amplifier (BLSA) equipped with offset compensation capability for low‐power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit‐line structure ...
J. Park +3 more
doaj +1 more source

A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors

Micromachines, 2019
A full three-dimensional technology-computer-aided-design-based reliability prediction model was proposed for dynamic random-access memory (DRAM) storage capacitors.
Woo Young Choi +5 more
doaj +1 more source

High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core Systems

IEEE Access, 2023
Modern DRAM devices’ performance and energy efficiency are significantly improved when the row-buffer locality is exploited properly. In multi-core architectures, however, the DRAM-based main memory banks used by the processing units, called cores,
Tareq A. Alawneh +3 more
doaj +1 more source

ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

IEEE Access, 2021
In sub-20 nm technologies, DRAM cells suffer from poor retention time. With the technology scaling, this problem tends to be worse, significantly increasing refresh power of DRAM.
Duy-Thanh Nguyen +4 more
doaj +1 more source

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Micromachines, 2020
Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM).
Hyeonjeong Kim +5 more
doaj +1 more source

Study of Row Hammer attack

网络与信息安全学报, 2018
The related technologies and defense methods of the current Row Hammer vulnerabilities were analyzed and summarized, and the security problems and possible precautions were pointed out.
WANG Wenwei, LIU Peishun
doaj +1 more source

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Nanomaterials, 2022
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using ...
Hee Dae An +11 more
doaj +1 more source

Novel Dual Work Function Buried Channel Array Transistor Process Design for Sub-17 nm DRAM

IEEE Access
This paper introduces the smallest dynamic random access memory (DRAM) cell, which was implemented using a new transistor structure, the dual work function - buried channel array transistor (DWF-BCAT).
Dong-Sik Park +7 more
doaj +1 more source

Improved Row Hammer and Passing Gate Effect Properties With Impurity Reduction of TiN Single Metal Word-Line in Modern DRAM

IEEE Access
As the feature size of the latest dynamic random access memory (DRAM) reaches the early 10 nm scale, it is becoming extremely challenging to build a robust word-line (WL).
Dongkyu Jang +7 more
doaj +1 more source

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

Micromachines, 2021
A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM).
Yejin Ha +3 more
doaj +1 more source

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