Results 21 to 30 of about 18,499 (235)
CoRR, 2016 This is a summary of the original paper, entitled "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture" which appears in HPCA ...
Donghyuk Lee +5 more
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An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution
IEEE Journal of the Electron Devices Society, 2018 This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance ...
Min Hee Cho +7 more
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Statistical DRAM modeling [PDF]
Proceedings of the International Symposium on Memory Systems, 2019 Cycle-accurate DRAM models are prevalent in today's computer architecture simulations. However, cycle-accurate models by design are time consuming and not scalable. In this paper, we present a statistical approach of DRAM latency modeling. Unlike previous works, our approach converts DRAM latency modeling into a classification problem and employ ...
Shang Li 0001, Bruce L. Jacob
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网络与信息安全学报, 2018 The related technologies and defense methods of the current Row Hammer vulnerabilities were analyzed and summarized, and the security problems and possible precautions were pointed out.
WANG Wenwei, LIU Peishun
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Sensors, 2021 With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5.
Duy-Thanh Nguyen +3 more
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IEEE Access, 2023 Modern DRAM devices’ performance and energy efficiency are significantly improved when the row-buffer locality is exploited properly. In multi-core architectures, however, the DRAM-based main memory banks used by the processing units, called cores,
Tareq A. Alawneh +3 more
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Inverted bit‐line sense amplifier with offset‐cancellation capability
Electronics Letters, 2016 An inverted bit‐line sense amplifier (BLSA) equipped with offset compensation capability for low‐power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit‐line structure ...
J. Park +3 more
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A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors
Micromachines, 2019 A full three-dimensional technology-computer-aided-design-based reliability prediction model was proposed for dynamic random-access memory (DRAM) storage capacitors.
Woo Young Choi +5 more
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ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM
IEEE Access, 2021 In sub-20 nm technologies, DRAM cells suffer from poor retention time. With the technology scaling, this problem tends to be worse, significantly increasing refresh power of DRAM.
Duy-Thanh Nguyen +4 more
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Nanomaterials, 2022 In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using ...
Hee Dae An +11 more
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