Results 161 to 170 of about 930 (217)

Body-raised double-gate structure for 1T DRAM

2009 IEEE Nanotechnology Materials and Devices Conference, 2009
Higher sensing margin and longer retention time are critical issues for commercializing 1T DRAM. In this paper, we propose a body-raised double-gate structure to improve sensing margin and retention time of 1T DRAM and confirm the improvements through 3D simulation. This structure shows about 20% higher sensing margin than the planar structure. We have
Garam Kim, Sang Wan Kim, Jae Young Song, Jong Pil Kim, Kyung-Chang Ryoo, Jeong-Hoon Oh, Jae Hyun Park, Hyun Woo Kim, Byung-Gook Park   +8 more
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Architecture Evaluation for Standalone and Embedded 1T-DRAM

2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2019
This paper analyzes different transistor architectures (inversion mode (IM), accumulation mode (AM) and junctionless (JL)) for standalone as well as embedded DRAM. The performance metrics (retention time (RT), sense margin (SM), current ratio (CR) and write time (WT)) of JL based 1T-DRAM can be improved through stacked JL (SJL) and core-shell (CS ...
Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti   +3 more
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A high density, high performance 1T DRAM cell

1982 International Electron Devices Meeting, 1982
This paper describes the structure and technology of a conventional two layer poly one transistor DRAM cell with special device enhancements to optimize its density, speed, and SER for 256K and low cost 64K DRAM products. The cell storage capacitance is enhanced by using a thin dielectric of 150A equivalent oxide thickness and a double-field oxidation ...
A. Mohsen, J. McCollum, R. Breivogel, S. Fu, E. Hamdy, D. McNeely, L. Patterson   +6 more
openaire   +1 more source

Novel Capacitor-Less 1T-DRAM Using MSD Effect

2006 IEEE international SOI Conferencee Proceedings, 2006
In this paper, we propose a different single-transistor capacitor-less DRAM which is operated at low drain voltage and enables low-power applications. The basic mechanism is the meta-stable dip (MSD) effect recently discovered (Bawedin et al., 2004, 2005). MSD gives rise to a hysteresis in ID(VG) curves and a dip in transconductance gm.
M. Bawedin, S. Cristoloveanu, D. Flandre
openaire   +1 more source

Performance Assessment of TFET Architectures as 1T-DRAM

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018
An assessment of Tunnel FET (TFET) architectures for capacitorless dynamic memory applications is presented through composite metrics to balance various trade-offs while regulating hole distribution to determine sense margin, retention time and current ratio.
Nupur Navlakha, Md. Hasan Raza Ansari, Jyi-Tsong Lin, Abhinav Kranti   +3 more
openaire   +1 more source

From SOI 1T-DRAMs to Unified Memory Concepts

MRS Proceedings, 2012
ABSTRACTThe typical architectures for single-transistor capacitorless dynamic random access memory (1T-DRAM) are reviewed. This memory takes advantage of floating-body effects in SOI-like devices. The principles of operation and the key mechanisms for memory programming and reading are described.
Sorin Cristoloveanu, Maryline Bawedin
openaire   +1 more source

Fully Depleted Polysilicon TFTs for Capacitorless 1T-DRAM

IEEE Electron Device Letters, 2009
A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n+ front gate and p+ back gate) shows a wider sensing current window than
Han, JW Han, Jin-Woo, Ryu, SW Ryu, Seong-Wan, Kim, DH Kim, Dong-Hyun, Kim, CJ Kim, Chung-Jin, Kim, SH Kim, Sung-Ho, Moon, DI Moon, Dong-Il, Choi, SJ Choi, Sung-Jin, Choi, YK Choi, Yang-Kyu   +7 more
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Gateless 1T-DRAM on n-Channel Bulk FinFETs

ECS Transactions, 2012
In this paper, one transistor floating body RAM is experimentally investigated on n-channel bulk FinFET transistors. Bipolar junction transistor (BJT) programming mode is used to write and read "1" while the forward biasing of the body-drain junction is used to write "0".
Maria G. Andrade, Luciano M. Almeida, Joao A. Martino, Marc Aoulaiche, Eddy Simoen, Cor Claeys   +5 more
openaire   +1 more source

Analysis and Evaluation of a BJT-Based 1T-DRAM

IEEE Electron Device Letters, 2010
A BJT-based 1T-DRAM that utilizes a latch process is analyzed in an experimental assessment. The experimental study reveals that undesired activation of a parasitic BJT by a high leakage current inhibits aggressive scaling of a BJT-based 1T-DRAM. Given the importance of choosing proper operation biases, the drain voltage that triggers the latch process
Choi, SJ Choi, Sung-Jin, Han, JW Han, Jin-Woo, Moon, DI Moon, Dong-Il, Choi, YK Choi, Yang-Kyu   +3 more
openaire   +2 more sources

A Novel 1T DRAM with Shell/Core Dual-Gate Architecture

2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020
This work proposes for the first time that the core-gate (CG) architectures are utilized as stand-alone and embedded capacitorless (one-transistor, 1T) dynamic random-access memory (DRAM) application with high scalability and strengthened high-temperature operation tolerance.
Md. Hasan Raza Ansari, Seongjae Cho
openaire   +1 more source