Results 171 to 180 of about 930 (217)

An Optically Assisted Program Method for Capacitorless 1T-DRAM

IEEE Transactions on Electron Devices, 2010
This work is aimed at a novel program method that is assisted by light for capacitorless 1T-DRAM based on parasitic bipolar junction transistor operation. Experimental results clearly show that a flash of light triggers a distinctive binary memory state in the capacitorless 1T-DRAM.
Moon, DI Moon, Dong-Il, Choi, SJ Choi, Sung-Jin, Han, JW Han, Jin-Woo, Choi, YK Choi, Yang-Kyu   +3 more
openaire   +2 more sources

Design and Analysis of Core-Gate Shell-Chanel 1T DRAM

2020 IEEE Silicon Nanoelectronics Workshop (SNW), 2020
The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices.
Md. Hasan Raza Ansari, Jae Yoon Lee, Seongjae Cho, Byung-Gook Park   +3 more
openaire   +1 more source

1T DRAM with Vertically Stacked n-Oxide-p Architecture

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018
In this work, vertically stackedn-oxide-p transistor architecture is explored as 1T-DRAM. The moderately dopedp type region is utilized to modulate (i) state currents flowing through the top n-type conduction region, and (ii) Retention Time (RT) through charges stored at the back surface of p-type storage region.
Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti   +3 more
openaire   +1 more source

TFET based 1T-DRAM: Physics, Significance and Trade-offs

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019
The work showcases device physics, the significance and trade-offs of DRAM metrics in a Tunnel Field Effect Transistor (TFET) based 1T dynamic memory. The analysis shows physical phenomenon that governs speed, Power (P), Energy (E), density, Sense Margin (SM), Current Ratio (CR), Retention Time (RT) and Delay (D) of DRAM.
Nupur Navlakha, Md. Hasan Raza Ansari, Abhinav Kranti   +2 more
openaire   +1 more source

The mystery of the Z²-FET 1T-DRAM memory

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017
We review the operation mechanisms of the Z2-FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.
Bawedin, M., El Dirani, H., Lee, K., Parihar, M., Lacord, J., Martinie, S., Le Royer, C., Mescot, Xavier, Barbé, Jean-Charles, Fonteneau, P., Galy, Ph., Gamiz, F., Navarro, C., Cheng, B., Asenov, A., Taur, Y., Cristoloveanu, S.   +16 more
openaire   +2 more sources

Two-sided read window observed on UTBOX SOI 1T-DRAM

28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
This paper analyzes the read windows of decananometer UTBOX SOI 1T-DRAM memory devices focusing on the mechanisms involved as a function of the applied gate voltage during the read operation. It will be demonstrated both experimentally and by simulation that a novel two-sided read window is possible where the two main effects present, GIDL and ...
Albert Nissimoff, Katia R. A. Sasaki, Marc Aoulaiche, Joao A. Martino, Eddy Simoen, Cor Claeys   +5 more
openaire   +1 more source

Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications

Solid-State Electronics, 2014
Abstract This work aims to analyze the retention time as a limiting factor for the application of 1T-DRAM cell in future CMOS nodes. Two approaches are proposed in order to improve the retention time: by the source/drain structure engineering or by applying a pulsed back gate bias. This work analyses the upgrade of the retention time by reducing the
K.R.A. Sasaki, T. Nicoletti, L.M. Almeida, S.D. dos Santos, A. Nissimoff, M. Aoulaiche, E. Simoen, C. Claeys, J.A. Martino   +8 more
openaire   +1 more source

A 20nm low-power triple-gate multibody 1T-DRAM cell

Proceedings of Technical Program of 2012 VLSI Technology, System and Application, 2012
The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple ...
F. Gamiz, N. Rodriguez, S. Cristoloveanu
openaire   +1 more source

Analysis of UTBOX 1T-DRAM Memory Cell at High Temperatures

ECS Transactions, 2011
This work investigates the behavior of Ultra Thin BOX (UTBOX) FDSOI devices used as a memory cell 1T-DRAM (single transistor dynamic random access memory) at high temperatures through 2D numerical simulations. The minimum drain voltage for the onset of the bipolar junction transistor (BJT) effect (VLatch) was obtained for various buried oxide thickness
Luciano M. Almeida, Katia R. Sasaki, Marc Aoulaiche, Eddy Simoen, Cor Claeys, João A. Martino   +5 more
openaire   +1 more source

3D Trigate 1T-DRAM Memory Cell for 2x nm Nodes

2012 4th IEEE International Memory Workshop, 2012
This paper presents a capacitor-less 1T DRAM cell based on a 3D Triple-gate multibody transistor with high scalability, low-power consumption, long retention time, non-destructive reading, and wide memory window. High performance is demonstrated on a 20nm channel length device, including '1' to '0' current ratio larger than 103 (with negligible '0 ...
Francisco Gamiz, Noel Rodriguez, Sorin Cristoloveanu   +2 more
openaire   +1 more source