Results 211 to 217 of about 930 (217)

Retention time enhancement in FD 1T-DRAM.

2013
Navarro, C., Bawedin, M., Romanjek, K., Cluzel, J., Andrieu, F., Sagnes, B., Cristoloveanu, S.   +6 more
openaire   +1 more source

DRAM Refresh Mechanisms, Penalties, and Trade-Offs

IEEE Transactions on Computers, 2016
exaly  

Ambipolar MISFET-Based 1T DRAM for Low-Power High-performance Applications

Veera Boopathy. E, L. Vigneash, Ramjan Begam A, Madhusudan Kulkarni, Kannadhasan S Kannadhasan S, Sheik Arafat. I   +5 more
openalex   +1 more source

Concepts of Capacitorless 1T-DRAM and Unified Memory on SOI

2017
Sorin Cristoloveanu, Maryline Bawedin
openaire   +1 more source

Characterization of a 1T-Floating Body DRAM Cell in Bulk Silicon MOSFETS for Cryogenic Memory Applications

Hongchao Guo, Yuanke Zhang, Yuefeng Chen, Hongling Sheng, Chi Fang, Guo‐Ping Guo, Chao Luo   +6 more
openalex   +1 more source

두 개의 게이트와 함몰 채널을 가지는 1T DRAM Cell

, 2010
김상완, 김가람, 심원보, 선민철, 김현우, 권대웅, 장지수, 김장현, 박의환, 이종호, 신형철, 박병국   +11 more
openalex  

Study of Capacitorless 1T-DRAM on Strained-Silicon-On-Insulator (sSOI) Substrate Using Impact Ionization and Gate-Induced-Dran-Leakage (GIDL) Programming

, 2011
정승민, 정홍배, Younghee Cheri Lee, 조원주   +3 more
openalex