Results 201 to 210 of about 101,310 (266)
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MESO-ADC: The ADC design using MESO device
Microelectronics Journal, 2021Abstract In this paper, we propose a new 3-bit ADC based on magnetoelectric spin–orbit (MESO) device. By adjusting the thickness of the magnetoelectric part of MESOs, the ADC possesses multiple switching thresholds for converting input voltages into magnetization state.
Junwei Zeng +6 more
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Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Oversampled ADC's are steadily reaching higher effective bandwidths and resolutions at lower power dissipation levels through the use of clever design techniques. The use of continuous time architecture enhances the system level usability by reducing the need for anti-aliasing filters.
Eric Naviasky, Hasnain Lakdawala
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Oversampled ADC's are steadily reaching higher effective bandwidths and resolutions at lower power dissipation levels through the use of clever design techniques. The use of continuous time architecture enhances the system level usability by reducing the need for anti-aliasing filters.
Eric Naviasky, Hasnain Lakdawala
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ADC trends and impact on SAR ADC architecture and analysis
2015 IEEE Custom Integrated Circuits Conference (CICC), 2015The performance of ADCs continues to improve with process scaling. For low to moderate resolutions, SAR ADCs deliver the best energy efficiency. Interleaved SAR converters have become popular for very high sampling speeds. The SAR assisted scheme has dramatically improved the energy efficiency of higher resolution pipeline ADCs.
Jeffrey Fredenburg, Michael P. Flynn
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“Split ADC” Background Linearization of VCO-Based ADCs
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs. Simulation results in a 45 nm CMOS process targeting 10 b and 12 b resolutions show ENOB of 9.58 b and 11.5 b, with convergence times for background calibration adaptation of 380 ms and 5.7 s, respectively. The background LMS procedure
John A. McNeill +2 more
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Increasing the ADC precision with oversampling in a flash ADC
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012This paper proposes new design to implement high resolution ADC using the idea of oversampling in flash ADCs. We used 6-bit Flash ADC with 65 times oversampling to gain a resolution of 12-bit Flash ADC. Conventional Flash ADCs are implemented using 2n comparators while proposed design requires only (26 + L(n)) comparators, Where L(n) is an exponential ...
Abdulrahman Abumurad, Kyusun Choi
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Evaluation of ADC Testing Systems Using ADC Transfer Standard
IEEE Transactions on Instrumentation and Measurement, 2004A transportable high stable reference AD device was designed and built for a comparison of systems for testing of the dynamic quality of ADCs or modules. Three different input modules enable its use in the frequency range up to 5 MHz. First, this paper refers to the results of the AD device application in the frequency range of the testing signal up to
Vladimír Haasz +2 more
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