Results 211 to 220 of about 101,310 (266)
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IEEE Transactions on Circuits and Systems II: Express Briefs, 2017
The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion ...
Chi-Hang Chan +5 more
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The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion ...
Chi-Hang Chan +5 more
openaire +1 more source
IEEE Transactions on Instrumentation and Measurement, 1996
The paper deals with a neural network-based approach for A/D converter (ADC) modeling. This approach is initially developed with reference to an ADC mathematical model, allowing the neural modeling to be properly setup. Subsequently, a neural model of a real ADC is identified and validated, highlighting the performance of the proposed approach in terms
BERNIERI A. +2 more
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The paper deals with a neural network-based approach for A/D converter (ADC) modeling. This approach is initially developed with reference to an ADC mathematical model, allowing the neural modeling to be properly setup. Subsequently, a neural model of a real ADC is identified and validated, highlighting the performance of the proposed approach in terms
BERNIERI A. +2 more
openaire +4 more sources
2009 IEEE Custom Integrated Circuits Conference, 2009
This session on Nyquest rate data converters has 7 exciting papers exploring the ranges of low power pipeline converters, calibration of SAR converters, ultra high speed flash converters, and high speed low power interleaved SAR converters.
Eric Naviasky, Ron Kapusta
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This session on Nyquest rate data converters has 7 exciting papers exploring the ranges of low power pipeline converters, calibration of SAR converters, ultra high speed flash converters, and high speed low power interleaved SAR converters.
Eric Naviasky, Ron Kapusta
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Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011
In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs.
Albert H. Chang +2 more
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In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs.
Albert H. Chang +2 more
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Multi-histogram ADC BIST System for ADC Linearity Testing
2013 22nd Asian Test Symposium, 2013This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC.
Koay Soon Chan +4 more
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A Hybrid ADC for High Resolution: The Zoom ADC
2017This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.
Gonen, B. (author) +3 more
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Measurement, 1999
The present paper begins by highlighting some difficulties encountered in the application of the testing algorithms described in the recent IEEE Std. 1241 DRAFT to commercial ADCs designed for audio application. In the experienced case study, the inaccurate knowledge of the DUT sampling rate made it unusable in the aforementioned testing algorithms ...
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The present paper begins by highlighting some difficulties encountered in the application of the testing algorithms described in the recent IEEE Std. 1241 DRAFT to commercial ADCs designed for audio application. In the experienced case study, the inaccurate knowledge of the DUT sampling rate made it unusable in the aforementioned testing algorithms ...
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Detailed analysis of a phase ADC
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010This paper presents for the first time a theoretical study of the second order effects of a 4-bit Phase-domain Analog-to-Digital Converter (ADC) circuit for QPSK demodulation and analyzes its benefits and drawbacks. The study encompasses the phase resolution, dynamic range and robustness of this circuit to circuit non-idealities and noise. Our analysis
Banerjee, B., Enz, C., Le Roux, E.
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Measurement of High-Speed ADCs
2017 IEEE Custom Integrated Circuits Conference (CICC), 2017High-speed high-resolution ADCs are challenging in design and measurement. High accuracy on data and clock input have to be ensured. To minimize nonlinearity, it is important to avoid signal-dependent errors. With these goals in mind, we discuss design trade-offs that have to be considered for high-resolution ADCs. Furthermore, a full measurement setup
Lukas Kull, Danny Luu
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Sub-ADC Architectures for Time-interleaved ADCs
2011Chapter 3 discusses the architecture of the sub-ADCs, which are used in the time-interleaved ADC. A Successive Approximation ADC (SA-ADC) can have a very good power efficiency, its sample-rate is however limited. In a conventional SA-ADC, the sample-rate is mainly limited by settling of the DAC. Overrange techniques can reduce the required DAC settling
Simon Louwsma, Ed van Tuijl, Bram Nauta
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