Results 261 to 270 of about 176,033 (310)

Multi-histogram ADC BIST System for ADC Linearity Testing

2013 22nd Asian Test Symposium, 2013
This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC.
Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong   +4 more
openaire   +1 more source

Measurement of High-Speed ADCs

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017
High-speed high-resolution ADCs are challenging in design and measurement. High accuracy on data and clock input have to be ensured. To minimize nonlinearity, it is important to avoid signal-dependent errors. With these goals in mind, we discuss design trade-offs that have to be considered for high-resolution ADCs. Furthermore, a full measurement setup
Lukas Kull, Danny Luu
openaire   +1 more source

A Hybrid ADC for High Resolution: The Zoom ADC

2017
This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.
Gonen, B. (author), van Veldhoven, Robert (author), Sebastiano, F. (author), Makinwa, K.A.A. (author)   +3 more
openaire   +3 more sources

The Zoom ADC: An Energy Efficient ADC for High Resolution

2021
Electronic ...
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A flash ADC with reduced complexity

IEEE Transactions on Industrial Electronics, 1995
An architecture for a flash ADC, with reduced circuit complexity is proposed. The design of this ADC is module oriented; a k,n-bit ADC is developed by just cascading k number of n-b flash modules. Making use of the proposed design approach, high resolution converters of 24 b and 32 b could easily be implemented with the low resolution flash modules. >
openaire   +3 more sources

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

IEEE Journal of Solid-State Circuits, 2021
Seung-Tak Ryu, Dong-Jin Chang, Michael Choi   +2 more
exaly  

Differentiation of Benign and Malignant Breast Lesions Using ADC Values and ADC Ratio in Breast MRI

Diagnostics, 2022
Katya Doykova, Katya Sapunarova, Silvia Tsvetkova   +2 more
exaly  

ADC

2021
openaire   +1 more source

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
Xiao Wang, Zhihua Wang, Fule Li
exaly  

ADCs

2021
openaire   +1 more source