Results 251 to 260 of about 176,033 (310)

ADC trends and impact on SAR ADC architecture and analysis

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015
The performance of ADCs continues to improve with process scaling. For low to moderate resolutions, SAR ADCs deliver the best energy efficiency. Interleaved SAR converters have become popular for very high sampling speeds. The SAR assisted scheme has dramatically improved the energy efficiency of higher resolution pipeline ADCs.
Jeffrey Fredenburg, Michael P. Flynn
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“Split ADC” Background Linearization of VCO-Based ADCs

IEEE Transactions on Circuits and Systems I: Regular Papers, 2015
A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs. Simulation results in a 45 nm CMOS process targeting 10 b and 12 b resolutions show ENOB of 9.58 b and 11.5 b, with convergence times for background calibration adaptation of 380 ms and 5.7 s, respectively. The background LMS procedure
John A. McNeill, Rabeeh Majidi, Jianping Gong   +2 more
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Evaluation of ADC Testing Systems Using ADC Transfer Standard

IEEE Transactions on Instrumentation and Measurement, 2004
A transportable high stable reference AD device was designed and built for a comparison of systems for testing of the dynamic quality of ADCs or modules. Three different input modules enable its use in the frequency range up to 5 MHz. First, this paper refers to the results of the AD device application in the frequency range of the testing signal up to
Vladimír Haasz, Jaroslav Roztocil, David Slepicka   +2 more
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ADC neural modeling

IEEE Transactions on Instrumentation and Measurement, 1996
The paper deals with a neural network-based approach for A/D converter (ADC) modeling. This approach is initially developed with reference to an ADC mathematical model, allowing the neural modeling to be properly setup. Subsequently, a neural model of a real ADC is identified and validated, highlighting the performance of the proposed approach in terms
BERNIERI A., DAPONTE P., GRIMALDI, Domenico   +2 more
openaire   +4 more sources

Metastablility in SAR ADCs

IEEE Transactions on Circuits and Systems II: Express Briefs, 2017
The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion ...
Chi-Hang Chan, Yan Zhu 0001, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins   +5 more
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Redundancy in SAR ADCs

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011
In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs.
Albert H. Chang, Hae-Seung Lee, Duane S. Boning   +2 more
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Nyquist rate ADCs

2009 IEEE Custom Integrated Circuits Conference, 2009
This session on Nyquest rate data converters has 7 exciting papers exploring the ranges of low power pipeline converters, calibration of SAR converters, ultra high speed flash converters, and high speed low power interleaved SAR converters.
Eric Naviasky, Ron Kapusta
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Increasing the ADC precision with oversampling in a flash ADC

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012
This paper proposes new design to implement high resolution ADC using the idea of oversampling in flash ADCs. We used 6-bit Flash ADC with 65 times oversampling to gain a resolution of 12-bit Flash ADC. Conventional Flash ADCs are implemented using 2n comparators while proposed design requires only (26 + L(n)) comparators, Where L(n) is an exponential ...
Abdulrahman Abumurad, Kyusun Choi
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Sub-ADC Architectures for Time-interleaved ADCs

2011
Chapter 3 discusses the architecture of the sub-ADCs, which are used in the time-interleaved ADC. A Successive Approximation ADC (SA-ADC) can have a very good power efficiency, its sample-rate is however limited. In a conventional SA-ADC, the sample-rate is mainly limited by settling of the DAC. Overrange techniques can reduce the required DAC settling
Simon Louwsma, Ed van Tuijl, Bram Nauta
openaire   +1 more source

ADC testing methods

Measurement, 1999
The present paper begins by highlighting some difficulties encountered in the application of the testing algorithms described in the recent IEEE Std. 1241 DRAFT to commercial ADCs designed for audio application. In the experienced case study, the inaccurate knowledge of the DUT sampling rate made it unusable in the aforementioned testing algorithms ...
openaire   +2 more sources