Results 31 to 40 of about 34,728 (307)
Design and analysis of hybrid 10T adder for low power applications
Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications.
D. Srinivas +2 more
doaj +1 more source
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA.
de Dinechin, Florent +2 more
openaire +2 more sources
Design and Analysis of an Approximate Adder with Hybrid Error Reduction
This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads.
Hyoju Seo, Yoon Seok Yang, Yongtae Kim
semanticscholar +1 more source
Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method.
C. Senthilpari +3 more
doaj +1 more source
Design and Implementation of Half Adder, Full Adder and CMOS Full Adder
In this paper, 1 bit full adder is designed in Microwind and DSCH. It is analysed using different implementation methods like AOI logic and using transmission gates. It is converted into an equivalent RC model to make the model simpler but less accurate for calculations.
openaire +1 more source
It has become quite apparent that over the last decade, youngsters have displayed an excessive use of and attachment to social media platforms, preeminently driven by a desire for online connection and interaction.
Zineb BENAYAD, Fatima Zohra ADDER
doaj +1 more source
Microfluidic time‐lapse analysis and reevaluation of the Bacillus subtilis cell cycle
Recent studies taking advantage of automated single‐cell time‐lapse analysis have reignited interest in the bacterial cell cycle. Several studies have highlighted alternative models, such as Sizer and Adder, which differ essentially in relation to ...
Seoungjun Lee +2 more
doaj +1 more source
A New Approach to Design of Cost-Efficient Reversible Quantum Dual-Full Adder and Subtractor [PDF]
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate.
Heranmoy Maity +7 more
doaj +1 more source
ABSTRACT Pediatric gastroenteropancreatic neuroendocrine neoplasms (GEP‐NENs) are extremely rare and clinically heterogeneous. Management has largely been extrapolated from adult practice. This European Standard Clinical Practice Guideline (ESCP), developed by the EXPeRT network in collaboration with adult NEN experts, provides (adult) evidence ...
Michaela Kuhlen +23 more
wiley +1 more source
Approximate Adder: Lower-Part or Adder
High-performance VLSI systems are essential in real-time applications, in order to increase the performance of the VLSI systems, an approximate computing technique is followed where the performance of the circuit is enhanced by trading off it with a slight loss in the accuracy.
openaire +1 more source

