FPGA IMPLEMENTATION OF HYBRID ADDER [PDF]
Proceedings on Engineering SciencesIn applications of Digital Electronics, the primary aim is precision, emphasizing accurate outcomes while concurrently minimizing power dissipation and latency.
K. Bala Sindhuri +5 more
doaj +2 more sources
Optimized low power hybrid adder architecture for OFDM in wireless communication [PDF]
Scientific ReportsThe contemporary wireless communication system makes full use of the available spectrum by making it possible to adapt to various channel situations. The extremely well-organized multi-carrier modulation technique of the orthogonal frequency division ...
T. Kalavathi Devi +7 more
doaj +2 more sources
A high‐performance full swing 1‐bit hybrid full adder cell
IET Circuits, Devices and Systems, 2022 This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs.
Shahbaz Hussain +3 more
doaj +2 more sources
Design of a low-delay 4-bit parallel prefix adder using QCA technology [PDF]
Scientific ReportsThis paper presents a novel low-delay 4-bit Parallel Prefix Adder (PPA) implemented as a multilayer circuit using Quantum Dot Cellular Automata (QCA) technology.
Tushar Niranjan +3 more
doaj +2 more sources
Modified vedic multiplier architecture using Nikhilam and Karatsuba algorithms with hybrid adders for enhanced performance [PDF]
Scientific ReportsHigh-performance computing applications rely on efficient multipliers, such as Digital Signal Processing (DSP) and Machine Learning (ML). This paper proposes an optimized 8 × 8 multiplier architecture by utilizing a Modified Vedic Nikhilam(VN) Sutra with
Sathiya A., Sridevi A.
doaj +2 more sources
Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation [PDF]
Scientific ReportsIn signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU ...
V. Thamizharasan, V. Parthipan
doaj +2 more sources
Low voltage high performance hybrid full adder
Engineering Science and Technology, an International Journal, 2016 This paper presents a low voltage and high performance 1-bit full adder designed with an efficient internal logic structure that leads to have a reduced Power Delay Product (PDP).
Pankaj Kumar, Rajender Kumar Sharma
doaj +3 more sources
Design and Implementation of Low-Complexity Multiple Symbol Detection Algorithm Using Hybrid Stochastic Computing in Aircraft Wireless Communications [PDF]
EntropyThe Multiple Symbol Detection (MSD) algorithm can effectively lower the demodulation threshold in Frequency Modulation (FM) technology, which is widely used in aircraft wireless communications due to its insensitivity to large Doppler shifts.
Yukai Liu +4 more
doaj +2 more sources
Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor [PDF]
Scientific ReportsThis paper introduces a new low-power pass transistor logic adder (PTLA) design utilizing 22 nm GNRFET (Graphene Nano Ribbon Field Effect Transistor) technology to enhance computing performance.
Sneha Arora +3 more
doaj +2 more sources
Certain investigation on hybrid neural network method for classification of ECG signal with the suitable a FIR filter [PDF]
Scientific ReportsThe Electrocardiogram (ECG) records are crucial for predicting heart diseases and evaluating patient’s health conditions. ECG signals provide essential peak values that reflect reliable health information. Analyzing ECG signals is a fundamental technique
Dinesh Kumar Jayaraman Rajendiran +3 more
doaj +2 more sources