Results 11 to 20 of about 706 (250)
Design of Wallace tree multiplier circuit using high performance and low power full adder [PDF]
E3S Web of Conferences, 2023 The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication.
Leela S. Naga +3 more
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Design and analysis of hybrid 10T adder for low power applications
e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023 Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications.
D. Srinivas +2 more
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SN Applied Sciences, 2021 Article Highlights Hybrid full adders offer better performance than single logic full adders Many existing full adder cells are not scalable Conventional Mirror CMOS full adder offers better performance than many recent full adders in wide adder ...
Mehedi Hasan +5 more
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Design of high speed hybrid carry select adder [PDF]
2013 3rd IEEE International Advance Computing Conference (IACC), 2013 The paper describes the power and area efficient carry select adder (CSA). Firstly, CSA is one of the fastest adders used in many data-processing systems to perform fast arithmetic operations. Secondly, CSA is intermediate between small areas but longer delay Ripple Carry Adder (RCA) and a larger area with shorter delay carry look-ahead adder.
Shivani Parmar, Kirat Pal Singh
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Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization
IEEE Access, 2020 Effective self-repairing can be achieved if the fault along with its exact location can be determined. In this paper, a self-repairing hybrid adder is proposed with fault localization.
Muhammad Ali Akbar +2 more
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Area Efficient Computing-in-Memory Architecture Using STT/SOT Hybrid Three Level Cell
IEEE Open Journal of Nanotechnology, 2022 Spintronic-based computing-in-memory (CiM) architecture has emerged as one of the efficient solutions to counter the latency/bandwidth bottleneck of conventional von-Neumann architecture.
Seema Dhull +3 more
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Design of Memristive Multiplier Based on Complementary Resistive Switch [PDF]
Jisuanji gongcheng, 2023 The existing memristive arithmetic logic primarily uses a single memristor as the storage unit, which is vulnerable to leakage currents in the memristor cross array and the high complexity of logic synthesis in a logic circuit design;consequently ...
LI Zhigang, CHEN Hui, LIU Peng, WU Jigang
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Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications
International Journal of Interactive Mobile Technologies (iJIM), 2020 In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high ...
Suguna, T., Janaki Rani, M.
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A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology
Majlesi Journal of Electrical Engineering, 2022 In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed.
Ali Ghorbani +3 more
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A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure
Ain Shams Engineering Journal, 2021 A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure.
Prashanth Barla +2 more
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