Results 21 to 30 of about 706 (250)
Design and implementation of hybrid logic based MAC unit using 45 nm technology
e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023 Digital signal processing algorithms, at times, necessitate the execution of a substantial quantity of mathematical operations to speed up and iterate upon a particular data set. Numerous digital signal processing (DSP) applications impose limitations on
Amgoth Laxman +2 more
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GDI based full adders for energy efficient arithmetic applications
Engineering Science and Technology, an International Journal, 2016 Addition is a vital arithmetic operation and acts as a building block for synthesizing all other operations. A high-performance adder is one of the key components in the design of application specific integrated circuits.
Mohan Shoba, Rangaswamy Nakkeeran
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A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic
IEEE Access, 2023 Spintronics has been garnering great success in resolving the shortcomings of conventional charge-based electronics and von-Neumann architecture by offering novel computational paradigms almost devoid of leakage effects and volatility issues of ...
Sreevatsan Rangaprasad +1 more
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64bit Hybrid Adder for ALU Design Applications
International Journal of Innovative Technology and Exploring Engineering, 2020 The Arithmetic Logic Unit is an important component of any Central Processing Unit. An improvement of the speed, area, and power consumption of an ALU directly promotes the performance of the system. Thus, optimization of the ALU design is necessary and for this reason several common adders such as the ripple carry adder, etc. and a proposed model of a
Hema Singaravelan*, Ravi S.
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From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review
IEEE Access, 2020 Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry.
Vinod Kumar Joshi +3 more
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Speed and energy optimized quasi-delay-insensitive block carry lookahead adder.
PLoS ONE, 2019 We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking ...
P Balasubramanian +2 more
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Design and Analysis of Hybrid Tree Multipliers for Reduction of Partial Products
Mehran University Research Journal of Engineering and Technology, 2018 This paper confers one of the three phases of tree multipliers, i.e. the Partial Product reduction phase. In this paper four types of hybrid tree multipliers are studied and proposed using parallel counters (full adders and half adders) for reduction of ...
Safia Bibi +2 more
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A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit
IEEE Access, 2019 Memristor-based digital logic circuits open new pathways for exploring advanced computing architectures, which provide a promising alternative to conventional IC technology.
Gongzhi Liu +4 more
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FEBS Letters, EarlyView.We present robust protocols for the preparation of supported lipid bilayers (SLBs) incorporating either Salmonella smooth LPS or outer membrane vesicles (OMVs). We use a combination of quartz crystal microbalance with dissipation (QCM‐D) and fluorescence microscopy to both characterize the SLBs of various compositions and to probe their interactions ...
Hudson P. Pace +6 more
wiley +1 more source
Scientific Reports, 2021 Integrated photonic devices or circuits that can execute both optical computation and optical data storage are considered as the building blocks for photonic computations beyond the von Neumann architecture.
Rajib Ratan Ghosh, Anuj Dhawan
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