Results 161 to 170 of about 84,601 (236)

All Digital Phase Locked Loop for Low Frequency Applications

2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018
This paper presents an architecture for the All Digital Phase Locked Loop (ADPLL) suitable for low frequency applications having an optimum area and power overhead. The described ADPLL consists of Phase Frequency Detector (PFD), Binary search module, Digital Controlled Oscillator (DCO) and Direct Digital Synthesizer (DDS) all of these blocks are ...
Pradyuman R Bissa, Kirti S Pande
openaire   +2 more sources

An Adaptive All-Digital Phase-Locked Loop Architecture for High-Stability MEMS Temperature-Compensated Clocks

International Conference on Information Communication and Management, 2023
Silicon-based Micro-Electro-Mechanical Systems (MEMS) clocks suffer from temperature drift, which severely affects the stability of their output frequency.
Xinyu Luo, Qianxu Fu, Yujie Zheng, Lu Tang   +3 more
semanticscholar   +1 more source

All-Digital Phase-Locked Loop in Single Flux Quantum Circuit Technology

IEEE transactions on applied superconductivity, 2022
Single flux quantum (SFQ) technology is one of the promising candidates for next generation very large-scale integration circuits. This article presents the design of an all-digital phase-locked loop (PLL) using the rapid SFQ technology with all the ...
Haolin Cong, Massoud Pedram
semanticscholar   +1 more source

Design of an All-Digital Phase-locked loop in a 130nm CMOS Process using open-source tools

2022 International Conference on Electronic Systems and Intelligent Computing (ICESIC), 2022
In this paper, an implementation of an ‘All-Digital Phase-Locked Loop’ has been elucidated, which includes the RTL level synthesis of the design, and the GDS level synthesis, obtained from the RTL to GDSII flow. The implemented design consists of a Phase
C. S, Nalinkumar S, Elavarasan P, Prakash P, Kasthuri P   +4 more
semanticscholar   +1 more source

System-level model of a two-step locking technique applied in an all-digital Phase-locked loop

International Conference on Modern Circuits and Systems Technologies, 2022
This paper proposes a system-level model of a new two-step locking technique for an all-digital phase-locked loop (ADPLL). The proposed design provides solutions for the trade-offs between the frequency resolution and locking range as well as between ...
S. Selvaraj, Erkan Bayram, R. Negra
semanticscholar   +1 more source

All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2021
In this paper, we study networks of coupled oscillators applied to the distributed synthesis of clock signals for large systems-on-chip. The oscillators are implemented as interconnected all-digital phase-locked loops (ADPLLs), which are asynchronous ...
Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina   +3 more
semanticscholar   +1 more source

A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized and Portable Architecture

IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, 2021
The article presents an all-digital phase-locked loop (ADPLL) design method based on standard cells. A new portable architecture introduced. Its motor is a fully synthesizable description of a digital controlled oscillator (DCO) with variable length ring
R. Khalirbaginov
semanticscholar   +1 more source

Design of a Configurable Digital Phase Locked Loop Circuit

2023 9th Annual International Conference on Network and Information Systems for Computers (ICNISC), 2023
With the increasing demand for communication technology in the application of AIoT products, digital phase-locked loops are increasingly being adopted in modern digital transmission technology due to their advantages such as wide frequency modulation ...
Xudong Zhou, Can Ba, Yuan Chu, Liang Wang, Hao Zhang   +4 more
semanticscholar   +1 more source

FPGA Implementation of True Random Number Generator Architecture Using All Digital Phase-Locked Loop

Journal of the Institution of Electronics and Telecommunication Engineers, 2021
This study is a unique approach for the design and implementation of True Random Number Generator (TRNG) using ADPLL, on Field-Programmable Gate Array (FPGA) board Artrix-7 (XC7A35T-CPG236-1) and the simulation was done on Vivado v.2015.2 design suite ...
Huirem Bharat Meitei, M. Kumar
semanticscholar   +1 more source

CMOS High-Resolution All-Digital Phase-Locked Loop

2003 46th Midwest Symposium on Circuits and Systems, 2006
The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD.
E. Mokhtari, M. Sawan
openaire   +2 more sources