Results 171 to 180 of about 84,601 (236)

Quantization Effects in All-Digital Phase-Locked Loops

IEEE Transactions on Circuits and Systems II: Express Briefs, 2007
This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO ...
P. Madoglio, M. Zanuso, LEVANTINO, SALVATORE, SAMORI, CARLO, LACAITA, ANDREA LEONARDO   +4 more
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Designs of All Digital Phase Locked Loop

2014 Recent Advances in Engineering and Computational Sciences (RAECS), 2014
Phase Locked Loop (PLL) is a feedback system that is configured as frequency multipliers, tracking generators, demodulators and clock recovery circuits. Today the most challenging requirement engineers' face is design of fast locking PLL with low jitter.
Aastha Singhal, Charu Madhu, Vijay Kumar
openaire   +1 more source

All-digital phase locked loop design assistant

2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015
An All-Digital Integer-N Phase Locked Loop (ADPLL) design assistant that models all the sub-blocks and noise sources in phase domain has been developed. For chosen top level design parameters, the generator designs the desired closed loop, open loop and digital loop filter characteristics of the ADPLL and analyzes the resulting phase noise performance ...
Yalcin Balcioglu, Gunhan Dundar
openaire   +1 more source

Direct digital synthesis-based all-digital phase-locked loop

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009
In this paper, we present an architecture for a PLL that is based on DDS and that can be implemented using all-digital components. The local oscillator is based on a DDS that is clocked by a local oscillator and that is synchronized to a crystal reference using a negative feedback which is similar to a PLL.
Benoit Vezant, Cedric Mansuy, Hung Tien Bui, Francois-Raymond Boyer   +3 more
openaire   +2 more sources

Automatic All-Digital Phase-Locked Loop System Design and optimization Tool

International Conference on Communication and Electronics Systems, 2020
An automated design and optimization tool for all digital phase locked-loop (ADPLL) system is presented in this paper. The ADPLL system design goal is to determine the digital loop filter (DLF) coefficients using analytic noise models and phase noise ...
Abdelrahman S. Moustafa, H. Omran, K. Sharaf   +2 more
semanticscholar   +1 more source

A CMOS implementation of controller based all digital phase locked loop (ADPLL)

, 2020
Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF ...
Vikas Balikai, H. Kittur
semanticscholar   +1 more source

Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2020
In this brief, we study jitter behavior in an event-driven self-sampled model of an All-Digital Phase-Locked Loop. We provide its steady-state analysis using simulations of a discrete-time model.
Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina   +3 more
semanticscholar   +1 more source

Response of an All Digital Phase-Locked Loop

IEEE Transactions on Communications, 1974
An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of ...
J. Garodnick, J. Greco, D. Schilling
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A Second-Order All-Digital Phase-Locked Loop

IEEE Transactions on Communications, 1974
A simple second-order digital phase-locked loop has been designed to synchronize itself to a square-wave subcarrier. Analysis and experimental performance are given for both acquisition behavior and steady-state phase error performance. In addition, the damping factor and the noise bandwidth are derived analytically. Although all the data are given for
J. Holmes, C. Tegnelia
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A 2.4-GHz Low-Power All-Digital Phase-Locked Loop

IEEE Journal of Solid-State Circuits, 2009
This paper presents an all-digital phase-locked loop (ADPLL) for the 2.4-GHz ISM band frequency synthesis. The ADPLL is built around a digitally controlled LC oscillator. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the
Xu, Liangge, Lindfors, Saska, Stadius, Kari, Ryynänen, Jussi   +4 more
openaire   +2 more sources