Results 181 to 190 of about 84,601 (236)

A 5GHz 90-nm CMOS all digital phase-locked loop

2009 IEEE Asian Solid-State Circuits Conference, 2009
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally ...
Ping Lu, Henrik Sjöland
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All digital phase-locked loop: concepts, design and applications

IEE Proceedings F Radar and Signal Processing, 1989
The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage-controlled oscillator, are explained. A second order DPLL is considered and analysed using the Z-transform technique. Implementation of the DPLL, based on the CMOS digital signal processor TMS 320C25, and the experimental ...
Y.R. Shayan, T. Le-Ngoc
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Research and Application of All Digital Phase-Locked Loop

2009 Second International Conference on Intelligent Networks and Intelligent Systems, 2009
The structure of an all digital phase-locked loop technology, ADPLL, is proposed in this paper. And the digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The time order graphs of all modules are presented.
Qiang Zhang, Kai Huang, Zuojun Liu, Zhigang Li   +3 more
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All-Digital Phase-Locked Loop for Optical Interconnect Applications

The 9th International Conference on Advanced Communication Technology, 2007
A novel all-digital phase-locked loop (ADPLL) is proposed and designed for chip-to-chip optical interconnect applications. The ADPLL is designed using the TSMC 0.18 mum CMOS technology. The core size of the ADPLL is 550times1040 mum2. The frequency range of the ADPLL is 3.0 - 3.4 GHz and power consumption is 18.67 mA with 1.8 V supply voltage.
Ngo Trong Hieu, Tae-Woo Lee, Hyo-Hoon Park   +2 more
openaire   +1 more source

All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping

IEEE International New Circuits and Systems Conference, 2019
In this paper, we study the propagation of timing error in a synchronous All-Digital Phase-Locked Loop network. The architecture of the network represents a linear array of oscillators, where the first oscillator is considered as the reference oscillator,
Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina   +3 more
semanticscholar   +1 more source

The Core Chip Design of Fast Locked All Digital Phase-locked Loop

International Conference on Information Communication and Management, 2019
This paper introduces a counter-based ADPLL (all-digital phase-locked loop) calibration module. The reference frequency of the all-digital phase-locked loop is 100MHz, and a bandwidth-adjustable filter is used. The circuit is based on a 40nm CMOS process
Yaqing Zhu, Lu Tang
semanticscholar   +1 more source

0.5V 160-MHz 260uW all digital phase-locked loop

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2009
A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with
null Jen-Chieh Liu, Hong-Yi Huang, null Wei-Bin Yang, Kuo-Hsing Cheng   +3 more
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Design of All-Digital Phase Locked Loop for Improved Frequency Lock Range

IEEE Conference on Systems, Process and Control, 2019
This paper presents the design and implementation of All Digital Phase Locked Loop (ADPLL) for improved lock range. FPGA implementation of improvised ADPLL is carried out on Xilinx Artix-7(xc7alStcpg236-1) chip.
Anjeleena Erm, Nidhi Toppo, D. Sugumar, P. Vanathi   +3 more
semanticscholar   +1 more source

All Digital Phase-Locked Loops

1998
In this chapter, we are going to extend our survey to loops that have do not have analog prototypes. Lindsey and Chie [1] performed a 1981 survey of digital PLLs that is recommended to the reader desiring additional architectures.
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An FPGA-Based Linear All-Digital Phase-Locked Loop

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters.
Martin Kumm, Harald Klingbeil, Peter Zipf   +2 more
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