Results 191 to 200 of about 84,601 (236)

An all digital phase locked loop fault tolerant clock

1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991
An implementation of a fault-tolerant clock is presented. The clock is quad redundant, designed according to a structured methodology that is tolerant to faults in any one of its four channels. This was achieved through the use of an all-digital phase-locked-loop (ADPLL) design that maintains synchronization to within 90 degrees between all nonfaulty ...
D.J. Van Alen, A.K. Somani
openaire   +1 more source

Optimum Digital Filter for High-Performance All-Digital Phase-Locked Loop

Applied Mechanics and Materials, 2012
The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain, and a systematic design procedure for ADPLL is presented. The pro-posed method not only estimates the output jitter of an ADPLL, but also finds the optimal filter pa-rameter minimizing the overall ADPLL timing jitter.
Hua Fang Sun, Xin Ning Liu, Xin Chen
openaire   +1 more source

A Simulink Model for All-Digital-Phase-Locked-Loop

2007 IEEE International Workshop on Radio-Frequency Integration Technology, 2007
A Simulink model for all-digital-phase-locked-look (ADPLL) is proposed in this paper. The study is based on ADPLL implemented in an all-digital RF transceiver. Simulation results in Simulink give the performance overview of the ADPLL.
Xiaoyan Wang, Yeung Bun Choi, Mingkyu Je, Wooi Gan Yeoh   +3 more
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A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

2009 International Symposium on VLSI Design, Automation and Test, 2009
In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications.
Hsuan-Jung Hsu, Shi-Yu Huang
openaire   +1 more source

Design of power efficient All Digital Phase Locked Loop (ADPLL)

2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016
This paper presents a power efficient design of All Digital Phase Locked Loop (ADPLL). The proposed ADPLL uses power optimized digital loop filter instead of the conventional one. The power optimization of digital loop filter is carried out with the aid of clock gating technique without degrading the performance of the overall system.
Nitesh Tripathi, Sambhu Nath Pradhan
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All digital phase‐locked loop with a wide locking range

Electronics and Communications in Japan (Part I: Communications), 1987
AbstractThe phase‐locked loop (PLL) is used widely in communication engineering as one of the key functions. Recently, some attempts have been made to construct a digital circuit for the phase‐locked loop. However, the common problems in those attempts is that there is a trade‐off between the locking range and the output phase jitter.
Hiroomi Hikawa, Nanning Zheng, Shinsaku Moris   +2 more
openaire   +1 more source

DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization

Asia Pacific Conference on Circuits and Systems, 2019
This paper proposes a hybrid time-voltage phase digitization technique in an all-digital phase-locked loop (ADPLL). To cover the required dynamic range of one oscillator period to measure the phase difference between clock edges of reference and feedback
V. Govindaraj, Jianglin Du, Yizhe Hu, T. Siriburanon, R. Staszewski   +4 more
semanticscholar   +1 more source

Novel Fractional Spur Relocation in All Digital Phase Locked Loops

2017 IEEE Wireless Communications and Networking Conference (WCNC), 2017
We present a new model that estimates the locations of the fractional spurs relative to the center carrier. Based on this model, we present a novel technique to mitigate the effect of fractional spurs generated in All-Digital Phase Locked Loops. Instead of using power-consuming spur cancellation algorithms, the proposed scheme enables to move the ...
Basak Can, Balvinder S. Bisla, Satwik Patnaik, Anthony Tsangaropoulos   +3 more
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A Novel Design of All Digital Phase Locked Loop for Wireless Applications

2019 International Conference on Innovative Sustainable Computational Technologies (CISCT), 2019
This work presented simulation, synthesis and implementation of the PLL for communication system. The requirement of all digital phase lock loop has needed basically because the microprocessor don't have sufficient procession power at such elevated ...
Aditya Raj, G. Patel, S. Tripathi, N. N. Das   +3 more
semanticscholar   +1 more source

All digital phase locked loop with input clock fail detector

2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 2015
All Digital Phase Locked Loops are widely used as clock generators in multiprocessor system on chips. An error detection system is crucial for such clock generators since it can be used to notify different processors to shut down so as to prevent the propagation of a faulty clock.
T V Aswathi, P Sathishkumar
openaire   +1 more source