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The Impact of Maximum Power Point Tracking Algorithms on Properties of On-Chip PV-Based Energy Harvester for IoT Devices. [PDF]

Sensors (Basel)
Hudec A, Stopjakova V, Ondica R, Potocny M, Nagy L.   +4 more
europepmc   +1 more source

Sequential monitoring and control of a silicon photonic coherent beam adder and analyzer. [PDF]

Sci Rep
De Gaetano S, Crico M, Ferrari G, Sampietro M, Morichetti F, Melloni A, Zanetto F.   +6 more
europepmc   +1 more source

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Reliability enhancement of analog-to-digital converters (ADCs)

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002
The reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. The reliability of these systems is affected by the ability of its constituent blocks to tolerate faults ...
Singh, M, Koren, I
openaire   +2 more sources

Incorporating fault tolerance in analog-to-digital converters (ADCs)

Proceedings International Symposium on Quality Electronic Design, 2003
The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity analysis is used to identify the most sensitive blocks which could then be redesigned for better reliability by incorporating fault tolerance. This paper illustrates the steps
Mandeep Singh, Israel Koren
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Domino ADC: A novel analog-to-digital converter architecture

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010
A novel analog-to-digital converter (ADC) architecture, named domino architecture, is introduced. The proposed idea can be taken as the continuous-time counterpart of SAR ADCs, and at the same time it resembles a series version of flash ADCs being implemented with much less circuit complexity and chip area.
Mohammad Takhti, Amir M. Sodagar, Reza Lotfi   +2 more
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Serial pixel analog-to-digital converter (ADC)

SPIE Proceedings, 2010
This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator.
openaire   +1 more source