Results 11 to 20 of about 115,723 (273)

Initial Measurements with the PETsys TOFPET2 ASIC Evaluation Kit and a Characterization of the ASIC TDC [PDF]

open access: yesIEEE Transactions on Radiation and Plasma Medical Sciences, 2018
For a first characterization, we used the two KETEK-PM3325-WB SiPMs each equipped with a 3x3x5 mm${}^3$ LYSO scintillation crystal provided with the PETsys TOFPET2 ASIC Evaluation Kit.
Gebhardt, Pierre   +4 more
core   +2 more sources

ASIC Clouds: Specializing the Datacenter

open access: yes2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016
GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance. In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost of ...
Magaki, Ikuo   +3 more
openaire   +3 more sources

ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols

open access: yesIEEE Access, 2018
Blockchain technology rapidly gained popularity based on its open and decentralized operation. Consensus protocol is the core mechanism of a blockchain network that securely maintains the distributed ledger from possible attacks from adversaries.
Hyungmin Cho
doaj   +2 more sources

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks [PDF]

open access: yesDesign Automation Conference, 2020
Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs). However, it remains an open problem how to integrate NAS with Application-
Lei Yang   +8 more
semanticscholar   +1 more source

A Comprehensive Study on the Timing Limits of the TOFPET2 ASIC and on Approaches for Improvements

open access: yesIEEE Transactions on Radiation and Plasma Medical Sciences, 2022
Novel electronic readout schemes of analog silicon photomultipliers (SiPMs) have shown impressive timing performance of $\gamma $ -detectors in positron emission tomography (PET).
V. Nadig   +6 more
semanticscholar   +1 more source

ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems [PDF]

open access: yesDesign Automation Conference, 2020
There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal
B. Prabakaran   +4 more
semanticscholar   +1 more source

A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System

open access: yesIEEE Journal of Solid-State Circuits, 2021
We present an area- and power-efficient application-specific integrated circuit (ASIC) for a miniaturized 3-D ultrasound system. The ASIC is designed to transmit pulse and receive echo through a 36-channel 2-D piezoelectric Micromachined Ultrasound ...
Jihee Lee   +7 more
semanticscholar   +1 more source

A Wearable Ultrasonic Neurostimulator—Part II: A 2D CMUT Phased Array System With a Flip-Chip Bonded ASIC

open access: yesIEEE Transactions on Biomedical Circuits and Systems, 2021
A 2D ultrasonic array is the ultimate form of a focused ultrasonic system, which enables electronically focusing beams in a 3D space. A 2D array is also a versatile tool for various applications such as 3D imaging, high-intensity focused ultrasound ...
C. Seok   +4 more
semanticscholar   +1 more source

800G DSP ASIC Design Using Probabilistic Shaping and Digital Sub-Carrier Multiplexing

open access: yesJournal of Lightwave Technology, 2020
The design of application-specific integrated circuits (ASIC) is at the core of modern ultra-high-speed transponders employing advanced digital signal processing (DSP) algorithms.
Han Sun   +34 more
semanticscholar   +1 more source

Hardware acceleration of number theoretic transform for zk‐SNARK

open access: yesEngineering Reports, EarlyView., 2023
An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao   +6 more
wiley   +1 more source

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