Results 121 to 130 of about 2,311 (170)

Hierarchical DSE for multi-ASIP platforms

2013 2nd Mediterranean Conference on Embedded Computing (MECO), 2013
This work proposes a hierarchical Design Space Exploration (DSE) for the design of multi-processor platforms targeted to specific applications with strict timing and area constraints. In particular, it considers platforms integrating multiple Application Specific Instruction Set Processors (ASIPs) and each ASIP is automatically synthesized and tuned ...
Laura Micconi, Rosilde Corvino, Deepak Gangadharan, Jan Madsen, Paul Pop, Lech Józwiak   +5 more
openaire   +2 more sources

Some of the next articles are maybe not open access.

Related searches:

Baseband ASIP design for SDR

China Communications, 2015
Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets.
Dake Liu
exaly   +2 more sources

ASIP for 5G and Beyond: Opportunities and Vision

IEEE Transactions on Circuits and Systems II: Express Briefs, 2021
The tutorial discusses application-specific instruction-set processors (ASIP) and their potential for the fifth generation (5G) and beyond 5G networks. ASIP is a class of customized processor, typically designed for a single or a small set of applications, incorporating flexibility of a software implementation and efficiency of a register transfer ...
Shahabuddin, Shahriar, Mammela, Aarne, Juntti, Markku, Silven, Olli   +4 more
openaire   +1 more source

Power reduction of ASIPs by distributing the workload on several ASIP-instances

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., 2006
In modern SoC designs, more and more application specific instruction-set processors (ASIPs) are used. They enable a trade off between the flexibility due to the software implementation of algorithms and hardware efficiency arising from the ASIP architecture which is optimized with respect to the application.
Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska   +4 more
openaire   +1 more source

ASIPs for artificial neural networks

2011 6th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI), 2011
Customized application-specific processors called ASIPs are becoming commonplace in contemporary embedded system designs. Neural networks are an interesting application for which an ASIP can be tailored to increase performance, lower power consumption and/or increase throughput.
Daniel Shapiro, Jonathan Parri, John-Marc Desmarais, Voicu Groza, Miodrag Bolic   +4 more
openaire   +1 more source

System design using ASIPs

Proceedings IEEE Symposium and Workshop on Engineering of Computer-Based Systems, 2002
This paper describes our current research in the field of systems design, trying to reach an Application Specific System Integration (ASIS). We try to go beyond circuit integration to reach systems integration, using Application Specific Processors (ASIPs) with different architectures. Our target system is based on industry applications.
Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin   +3 more
openaire   +1 more source

Synthesis of ASIPs for DSP algorithms

Integration, 1999
ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures ...
Ramanathan, S, Visvanathan, V, Nandy, SK
openaire   +2 more sources

Evaluation of ASIPs Design with LISATek

2008
This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE ...
Muhammad Rashid 0001, Ludovic Apvrille, Renaud Pacalet   +2 more
openaire   +1 more source

Symbolic binding for clustered VLIW ASIPs

Proceedings 2000 International Conference on Computer Design, 2002
The paper proposes a symbolic framework to address the binding problem for embedded VLIW ASIPs. Alternative objective functions as well as trade-offs relevant to the binding phase of code generation for embedded processors are presented and discussed.
Satish Pillai, Margarida F. Jacome
openaire   +1 more source

Exploring storage organization in ASIP synthesis

Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003
Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster ...
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar   +2 more
openaire   +1 more source