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Evaluation of ASIPs Design with LISATek
2008This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE ...
Muhammad Rashid 0001 +2 more
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2011
ASIPs represent a growing trend of application oriented processor specialization for computationally intensive embedded applications. The first micro-processors – Intel 4004, TI TMS 1000 and Central Air Data Computer (CADC) – designed way back in the early 1970s were mostly intended for general purpose usage.
Kingshuk Karuri, Rainer Leupers
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ASIPs represent a growing trend of application oriented processor specialization for computationally intensive embedded applications. The first micro-processors – Intel 4004, TI TMS 1000 and Central Air Data Computer (CADC) – designed way back in the early 1970s were mostly intended for general purpose usage.
Kingshuk Karuri, Rainer Leupers
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Symbolic binding for clustered VLIW ASIPs
Proceedings 2000 International Conference on Computer Design, 2002The paper proposes a symbolic framework to address the binding problem for embedded VLIW ASIPs. Alternative objective functions as well as trade-offs relevant to the binding phase of code generation for embedded processors are presented and discussed.
Satish Pillai, Margarida F. Jacome
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Exploring storage organization in ASIP synthesis
Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster ...
Manoj Kumar Jain +2 more
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2011
In this chapter, we will attempt to provide a thorough background on profiling for ASIP design. Readers may recall that profiling constitutes one of the two primary components of the processor design-flow presented in Sect. 3.4 of the previous chapter.
Kingshuk Karuri, Rainer Leupers
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In this chapter, we will attempt to provide a thorough background on profiling for ASIP design. Readers may recall that profiling constitutes one of the two primary components of the processor design-flow presented in Sect. 3.4 of the previous chapter.
Kingshuk Karuri, Rainer Leupers
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Loop Acceleration Exploration for ASIP Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012Design space exploration is a delicate process whose success lays on the designers' shoulders. It is often based on a trial-and-error approach. Some basic metrics can be used to guide this process. In this paper, we explore accelerating loops from C-based specifications.
Mame Maria Mbaye +3 more
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ASIP design methodologies: survey and issues
VLSI Design 2001. Fourteenth International Conference on VLSI Design, 2002Interest in synthesis of Application Specific Instruction Processors or ASIPs has increased considerably and a number of methodologies have been proposed in the last decade. This paper attempts to survey the state of the art in this area and identifies some issues which need to be addressed.
Manoj Kumar Jain +2 more
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FPGA Prototyping and Accelerated Verification of ASIPs
2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted
Jakub Podivinsky +3 more
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2009
The design of an ASIP is a challenging task due to the large number of design options. The competing design decisions such as flexibility, performance, and energy consumption need to be weighted against each other to reach the optimal point in the entire design space.
Manuel Hohenauer, Rainer Leupers
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The design of an ASIP is a challenging task due to the large number of design options. The competing design decisions such as flexibility, performance, and energy consumption need to be weighted against each other to reach the optimal point in the entire design space.
Manuel Hohenauer, Rainer Leupers
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Hierarchical DSE for multi-ASIP platforms
2013 2nd Mediterranean Conference on Embedded Computing (MECO), 2013This work proposes a hierarchical Design Space Exploration (DSE) for the design of multi-processor platforms targeted to specific applications with strict timing and area constraints. In particular, it considers platforms integrating multiple Application Specific Instruction Set Processors (ASIPs) and each ASIP is automatically synthesized and tuned ...
Laura Micconi +5 more
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