Results 131 to 140 of about 2,311 (170)

The ASIP Design Space

2011
ASIPs represent a growing trend of application oriented processor specialization for computationally intensive embedded applications. The first micro-processors – Intel 4004, TI TMS 1000 and Central Air Data Computer (CADC) – designed way back in the early 1970s were mostly intended for general purpose usage.
Kingshuk Karuri, Rainer Leupers
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Loop Acceleration Exploration for ASIP Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012
Design space exploration is a delicate process whose success lays on the designers' shoulders. It is often based on a trial-and-error approach. Some basic metrics can be used to guide this process. In this paper, we explore accelerating loops from C-based specifications.
Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre   +3 more
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ASIP design methodologies: survey and issues

VLSI Design 2001. Fourteenth International Conference on VLSI Design, 2002
Interest in synthesis of Application Specific Instruction Processors or ASIPs has increased considerably and a number of methodologies have been proposed in the last decade. This paper attempts to survey the state of the art in this area and identifies some issues which need to be addressed.
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar   +2 more
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FPGA Prototyping and Accelerated Verification of ASIPs

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted
Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek   +3 more
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Profiling for ASIP Design

2011
In this chapter, we will attempt to provide a thorough background on profiling for ASIP design. Readers may recall that profiling constitutes one of the two primary components of the processor design-flow presented in Sect. 3.4 of the previous chapter.
Kingshuk Karuri, Rainer Leupers
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PEAS-III: an ASIP design environment

Proceedings 2000 International Conference on Computer Design, 2002
In this paper, an architectural level processor design environment PEAS-III is proposed. Pipelined processors designed by this system can include multi-cycle operation, delayed branch and external interrupt. The data path and control logic of the processor are generated from the clock based micro-operation description of instructions. The ease of large
Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi   +6 more
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ASIP Design Methodology

2009
The design of an ASIP is a challenging task due to the large number of design options. The competing design decisions such as flexibility, performance, and energy consumption need to be weighted against each other to reach the optimal point in the entire design space.
Manuel Hohenauer, Rainer Leupers
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Automatic Generation of Memory Interfaces for ASIPs

International Journal of Embedded and Real-Time Communication Systems, 2010
With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of ...
David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr   +6 more
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Dynamically Adapted Low Power ASIPs

2009
New generations of embedded devices, following the trend found in personal computers, are becoming computationally powerful. A current embedded scenario presents a large amount of complex and heterogeneous functionalities, which have been forcing designers to create novel solutions to increase the performance of embedded processors while, at the same ...
Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro   +2 more
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Design of an ASIP IDEA crypto processor

2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, 2011
A New architecture is presented in this paper for International Data Encryption Algorithm based on Application Specific Instruction set Processors platform. Designing process is explained comprehensively for all the main components within the crypto processor core.
Reza Faghih Mirzaee, Mohammad Eshghi
openaire   +1 more source