Results 91 to 100 of about 7,553,652 (107)
Some of the next articles are maybe not open access.

REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches

IEEE Transactions on Magnetics, 2019
Amir Mahdi Hosseini Monazzah   +2 more
exaly  

Errors in Management of Head and Neck Tumors

Ca-A Cancer Journal for Clinicians, 1968
Richard A. Larson   +2 more
exaly  

Detection of Cervical Neoplasia: Reducing the Risk of Error

Ca-A Cancer Journal for Clinicians, 1974
Richard F Mattingly
exaly  

A New Asymmetric 6T SRAM Cell With a Write Assist Technique in 65 nm CMOS Technology

Microelectronics Journal, 2014
Farshad Moradi   +2 more
exaly  

A Software-Based NVM Emulator Supporting Read/Write Asymmetric Latencies

IEICE Transactions on Information and Systems, 2019
Atsushi Koshiba   +2 more
exaly  

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
Kaushik Roy   +2 more
exaly  

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