Results 141 to 150 of about 7,117,098 (159)

REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches

IEEE Transactions on Magnetics, 2019
Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Ensieh Aliagha   +2 more
exaly  

Asymmetric focused-ion-beam trimming of longitudinal and perpendicular write heads

IEEE Transactions on Magnetics, 2003
P A A van der Heijden
exaly  

Weighted Error Correcting Code (WECC) for Asymmetric Errors in STT-MRAM

2022
Yanfeng Jiang, Qiguang Wang
exaly  

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

IEICE Transactions on Information and Systems, 2019
Atsushi Koshiba, Ryousei Takano, Mitaro Namiki   +2 more
exaly  

A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

Microelectronics Journal, 2014
Farshad Moradi, Hooman Farkhani, Ali Peiravi   +2 more
exaly  

Data Allocation Algorithm based on Write and Read Frequency for Double Asymmetric-latency SCM SSD

2020
Ken Takeuchi
exaly  

Dependence of Write-Window on Write Error Rates in Bit Patterned Media

IEEE Transactions on Magnetics, 2010
Jim J Miles
exaly  

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim   +2 more
exaly  

Dependence of Voltage and Size on Write Error Rates in Spin-Transfer Torque Magnetic Random-Access Memory

IEEE Magnetics Letters, 2016
Jonathan Sun, Daniel Worledge
exaly  

Write error rates of in-plane spin-transfer-torque random access memory calculated from rare-event enhanced micromagnetic simulations

Journal of Magnetism and Magnetic Materials, 2018
Priyamvada Jadaun, Tanmoy Pramanik, Sanjay Banerjee   +2 more
exaly