Results 191 to 200 of about 3,221 (210)

Weighted Error Correcting Code (WECC) for Asymmetric Errors in STT-MRAM

2022
Qiguang Wang, Yanfeng Jiang
exaly  

REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches

IEEE Transactions on Magnetics, 2019
Ensieh Aliagha, Amir Mahdi Hosseini Monazzah, Hamed Farbeh   +2 more
exaly  

A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

Microelectronics Journal, 2014
Hooman Farkhani, Ali Peiravi, Farshad Moradi   +2 more
exaly  

Data Allocation Algorithm based on Write and Read Frequency for Double Asymmetric-latency SCM SSD

2020
Ken Takeuchi
exaly  

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

IEICE Transactions on Information and Systems, 2019
Atsushi Koshiba, Takahiro Hirofuchi, Ryousei Takano   +2 more
exaly  

Dependence of Voltage and Size on Write Error Rates in Spin-Transfer Torque Magnetic Random-Access Memory

IEEE Magnetics Letters, 2016
J Z Sun, D C Worledge
exaly  

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim   +2 more
exaly  

AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches

IEEE Transactions on Emerging Topics in Computing, 2019
Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah   +2 more
exaly  

Capacity Enhancement of Asymmetric Multi-Level Cell (MLC) NAND Flash Memory using Write Voltage Optimization

2019
Watid Phakphisut, Pornchai Supnithi
exaly  

Write error rates of in-plane spin-transfer-torque random access memory calculated from rare-event enhanced micromagnetic simulations

Journal of Magnetism and Magnetic Materials, 2018
Tanmoy Pramanik, Urmimala Roy, Priyamvada Jadaun   +2 more
exaly